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公开(公告)号:US07981791B2
公开(公告)日:2011-07-19
申请号:US12202132
申请日:2008-08-29
申请人: Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey , Christiaan J. Werkhoven
发明人: Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey , Christiaan J. Werkhoven
IPC分类号: H01L21/4763
CPC分类号: C23C16/029 , C23C16/34 , C23C16/401 , C23C16/403 , C23C16/405 , C23C16/452 , C23C16/45529 , C23C16/45531 , C23C16/45534 , C30B25/14 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02189 , H01L21/02194 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28562 , H01L21/3141 , H01L21/3145 , H01L21/31612 , H01L21/3162 , H01L21/31641 , H01L21/3185 , H01L21/76846 , H01L21/76873 , H01L21/76879 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2221/1089
摘要: Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces. In some embodiments additional seed layers or additional transition layers are provided.
摘要翻译: 通过原子层沉积形成薄膜,由此膜的组成可以在包括自限制化学的交替脉冲的循环期间从单层变为单层。 在所示实施例中,在循环过程中引入了不同量的杂质源。 因此,即使对于非常薄的层也提供了梯度栅极电介质。 薄的2nm的栅极电介质可以从纯氧化硅到氧氮化物变化为氮化硅。 类似地,栅极电介质可以从氧化铝变化为氧化铝和较高电介质材料(例如,ZrO 2)到纯高k材料并返回到氧化铝的混合物。 在另一个实施例中,金属氮化物(例如,WN)首先形成为用于衬里双镶嵌沟槽和通孔的屏障。 在交替沉积工艺期间,铜可以被引入,例如分开的脉冲,并且铜源脉冲可以逐渐增加频率,形成过渡区域,直到在上表面形成纯铜。 有利的是,这些和各种其他情况下的分级组合物有助于避免诸如在尖锐材料界面处可能发生的蚀刻速率控制,电迁移和非欧姆电接触等问题。 在一些实施例中,提供了额外的种子层或附加的过渡层。
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公开(公告)号:US07419903B2
公开(公告)日:2008-09-02
申请号:US11106220
申请日:2005-04-13
申请人: Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey
发明人: Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey
IPC分类号: H01L21/4763
CPC分类号: C23C16/029 , C23C16/34 , C23C16/401 , C23C16/403 , C23C16/405 , C23C16/452 , C23C16/45529 , C23C16/45531 , C23C16/45534 , C30B25/14 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02189 , H01L21/02194 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28562 , H01L21/3141 , H01L21/3145 , H01L21/31612 , H01L21/3162 , H01L21/31641 , H01L21/3185 , H01L21/76846 , H01L21/76873 , H01L21/76879 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2221/1089
摘要: Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces. In some embodiments additional seed layers or additional transition layers are provided.
摘要翻译: 通过原子层沉积形成薄膜,由此膜的组成可以在包括自限制化学的交替脉冲的循环期间从单层变为单层。 在所示实施例中,在循环过程中引入了不同量的杂质源。 因此,即使对于非常薄的层也提供了渐变栅极电介质。 薄的2nm的栅极电介质可以从纯氧化硅到氧氮化物变化为氮化硅。 类似地,栅极电介质可以从氧化铝到氧化铝和较高介电材料(例如ZrO 2)的混合物变化为纯高k材料并返回到氧化铝。 在另一个实施例中,金属氮化物(例如,WN)首先形成为用于衬里双镶嵌沟槽和通孔的屏障。 在交替沉积工艺期间,铜可以被引入,例如分开的脉冲,并且铜源脉冲可以逐渐增加频率,形成过渡区域,直到在上表面形成纯铜。 有利的是,这些和各种其他情况下的分级组合物有助于避免诸如在尖锐材料界面处可能发生的蚀刻速率控制,电迁移和非欧姆电接触等问题。 在一些实施例中,提供了额外的种子层或附加的过渡层。
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公开(公告)号:US20090068832A1
公开(公告)日:2009-03-12
申请号:US12202132
申请日:2008-08-29
申请人: Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey , Christrian J. Werkhoven
发明人: Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey , Christrian J. Werkhoven
IPC分类号: H01L21/4763
CPC分类号: C23C16/029 , C23C16/34 , C23C16/401 , C23C16/403 , C23C16/405 , C23C16/452 , C23C16/45529 , C23C16/45531 , C23C16/45534 , C30B25/14 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02189 , H01L21/02194 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28562 , H01L21/3141 , H01L21/3145 , H01L21/31612 , H01L21/3162 , H01L21/31641 , H01L21/3185 , H01L21/76846 , H01L21/76873 , H01L21/76879 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2221/1089
摘要: Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces. In some embodiments additional seed layers or additional transition layers are provided.
摘要翻译: 通过原子层沉积形成薄膜,由此膜的组成可以在包括自限制化学的交替脉冲的循环期间从单层变为单层。 在所示实施例中,在循环过程中引入了不同量的杂质源。 因此,即使对于非常薄的层也提供了梯度栅极电介质。 薄的2nm的栅极电介质可以从纯氧化硅到氧氮化物变化为氮化硅。 类似地,栅极电介质可以从氧化铝变化为氧化铝和较高电介质材料(例如,ZrO 2)到纯高k材料并返回到氧化铝的混合物。 在另一个实施例中,金属氮化物(例如,WN)首先形成为用于衬里双镶嵌沟槽和通孔的屏障。 在交替沉积工艺期间,铜可以被引入,例如分开的脉冲,并且铜源脉冲可以逐渐增加频率,形成过渡区域,直到在上表面形成纯铜。 有利的是,这些和各种其他情况下的分级组合物有助于避免诸如在尖锐材料界面处可能发生的蚀刻速率控制,电迁移和非欧姆电接触等问题。 在一些实施例中,提供了额外的种子层或附加的过渡层。
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公开(公告)号:US20110256718A1
公开(公告)日:2011-10-20
申请号:US13079562
申请日:2011-04-04
申请人: Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey , Christiaan J. Werkhoven
发明人: Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey , Christiaan J. Werkhoven
IPC分类号: H01L21/285
CPC分类号: C23C16/029 , C23C16/34 , C23C16/401 , C23C16/403 , C23C16/405 , C23C16/452 , C23C16/45529 , C23C16/45531 , C23C16/45534 , C30B25/14 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02189 , H01L21/02194 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28562 , H01L21/3141 , H01L21/3145 , H01L21/31612 , H01L21/3162 , H01L21/31641 , H01L21/3185 , H01L21/76846 , H01L21/76873 , H01L21/76879 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2221/1089
摘要: Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces. In some embodiments additional seed layers or additional transition layers are provided.
摘要翻译: 通过原子层沉积形成薄膜,由此膜的组成可以在包括自限制化学的交替脉冲的循环期间从单层变为单层。 在所示实施例中,在循环过程中引入了不同量的杂质源。 因此,即使对于非常薄的层也提供了梯度栅极电介质。 薄的2nm的栅极电介质可以从纯氧化硅到氧氮化物变化为氮化硅。 类似地,栅极电介质可以从氧化铝变化为氧化铝和较高电介质材料(例如,ZrO 2)到纯高k材料并返回到氧化铝的混合物。 在另一个实施例中,金属氮化物(例如,WN)首先形成为用于衬里双镶嵌沟槽和通孔的屏障。 在交替沉积工艺期间,铜可以被引入,例如分开的脉冲,并且铜源脉冲可以逐渐增加频率,形成过渡区域,直到在上表面形成纯铜。 有利的是,这些和各种其他情况下的分级组合物有助于避免诸如在尖锐材料界面处可能发生的蚀刻速率控制,电迁移和非欧姆电接触等问题。 在一些实施例中,提供了额外的种子层或附加的过渡层。
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公开(公告)号:US20050181555A1
公开(公告)日:2005-08-18
申请号:US11106220
申请日:2005-04-13
申请人: Suvi Haukka , Ivo Raaijmakers , Wei Li , Juhana Kostamo , Hessel Sprey , Christiaan Werkhoven
发明人: Suvi Haukka , Ivo Raaijmakers , Wei Li , Juhana Kostamo , Hessel Sprey , Christiaan Werkhoven
IPC分类号: C23C16/02 , C23C16/34 , C23C16/40 , C23C16/44 , C23C16/455 , C23C16/48 , C30B25/14 , H01L21/28 , H01L21/285 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/768 , H01L29/51 , H01L21/8238
CPC分类号: C23C16/029 , C23C16/34 , C23C16/401 , C23C16/403 , C23C16/405 , C23C16/452 , C23C16/45529 , C23C16/45531 , C23C16/45534 , C30B25/14 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02189 , H01L21/02194 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28562 , H01L21/3141 , H01L21/3145 , H01L21/31612 , H01L21/3162 , H01L21/31641 , H01L21/3185 , H01L21/76846 , H01L21/76873 , H01L21/76879 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2221/1089
摘要: Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces. In some embodiments additional seed layers or additional transition layers are provided.
摘要翻译: 通过原子层沉积形成薄膜,由此膜的组成可以在包括自限制化学的交替脉冲的循环期间从单层变为单层。 在所示实施例中,在循环过程中引入了不同量的杂质源。 因此,即使对于非常薄的层也提供了梯度栅极电介质。 薄的2nm的栅极电介质可以从纯氧化硅到氧氮化物变化为氮化硅。 类似地,栅极电介质可以从氧化铝到氧化铝和较高介电材料(例如ZrO 2)的混合物变化为纯高k材料并返回到氧化铝。 在另一个实施例中,金属氮化物(例如,WN)首先形成为用于衬里双镶嵌沟槽和通孔的屏障。 在交替沉积工艺期间,铜可以被引入,例如分开的脉冲,并且铜源脉冲可以逐渐增加频率,形成过渡区域,直到在上表面形成纯铜。 有利的是,这些和各种其他情况下的分级组合物有助于避免诸如在尖锐材料界面处可能发生的蚀刻速率控制,电迁移和非欧姆电接触等问题。 在一些实施例中,提供了额外的种子层或附加的过渡层。
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公开(公告)号:US20050092249A1
公开(公告)日:2005-05-05
申请号:US10991556
申请日:2004-11-18
申请人: Olli Kilpela , Ville Saanila , Wei-Min Li , Kai-Erik Elers , Juhana Kostamo , Ivo Raaijmakers , Ernst Granneman
发明人: Olli Kilpela , Ville Saanila , Wei-Min Li , Kai-Erik Elers , Juhana Kostamo , Ivo Raaijmakers , Ernst Granneman
IPC分类号: C23C16/44 , C23C16/452 , C23C16/455 , C23C16/507 , C23C16/509 , C23C16/00
CPC分类号: C23C16/45544 , C23C16/4412 , C23C16/452 , C23C16/45514 , C23C16/45536 , C23C16/45565 , C23C16/45589 , C23C16/507 , C23C16/509
摘要: Various reactors for growing thin films on a substrate by subjecting the substrate to alternately repeated surface reactions of vapor-phase reactants are disclosed. In one embodiment, the reactor comprises a reaction chamber. A showerhead plate divides the reaction chamber into upper and lower parts. A first precursor is directed towards the lower half of the reaction chamber and a second precursor is directed towards the upper half of the reaction chamber. The substrate is disposed within the lower half of the reaction chamber. The showerhead plate includes plurality passages such that the upper half is in communication with the lower half of the reaction chamber. In another arrangement, the upper half of the reaction chamber defines a plasma cavity in which in-situ radicals are formed. In yet another arrangement, the reaction chamber includes a shutter plate, which is configured to selectively open and close the passages in the showerhead plate. In other arrangements, the showerhead plate is arranged to modify the local flow patterns of the gases flowing through the reaction chamber.
摘要翻译: 公开了用于通过使衬底经历气相反应物的交替重复表面反应而在衬底上生长薄膜的各种反应器。 在一个实施方案中,反应器包括反应室。 喷头板将反应室分成上部和下部。 第一前体指向反应室的下半部分,第二前体指向反应室的上半部分。 基板设置在反应室的下半部内。 喷头板包括多个通道,使得上半部分与反应室的下半部连通。 在另一种布置中,反应室的上半部限定了其中形成原位自由基的等离子体腔。 在另一种布置中,反应室包括挡板,其被构造成选择性地打开和关闭喷头板中的通道。 在其他布置中,喷头板被布置成改变流过反应室的气体的局部流动模式。
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公开(公告)号:US06820570B2
公开(公告)日:2004-11-23
申请号:US10222005
申请日:2002-08-14
申请人: Olli Kilpela , Ville Saanila , Wei-Min Li , Kai-Erik Elers , Juhana Kostamo , Ivo Raaijmakers , Ernst Granneman
发明人: Olli Kilpela , Ville Saanila , Wei-Min Li , Kai-Erik Elers , Juhana Kostamo , Ivo Raaijmakers , Ernst Granneman
IPC分类号: C23C16509
CPC分类号: C23C16/45544 , C23C16/4412 , C23C16/452 , C23C16/45514 , C23C16/45536 , C23C16/45565 , C23C16/45589 , C23C16/507 , C23C16/509
摘要: Various reactors for growing thin films on a substrate by subjecting the substrate to alternately repeated surface reactions of vapor-phase reactants are disclosed. In one embodiment, the reactor comprises a reaction chamber. A showerhead plate divides the reaction chamber into upper and lower parts. A first precursor is directed towards the lower half of the reaction chamber and a second precursor is directed towards the upper half of the reaction chamber. The substrate is disposed within the lower half of the reaction chamber. The showerhead plate includes plurality passages such that the upper half is in communication with the lower half of the reaction chamber. In another arrangement, the upper half of the reaction chamber defines a plasma cavity in which in-situ radicals are formed. In yet another arrangement, the reaction chamber includes a shutter plate, which is configured to selectively open and close the passages in the showerhead plate. In other arrangements, the showerhead plate is arranged to modify the local flow patterns of the gases flowing through the reaction chamber.
摘要翻译: 公开了用于通过使衬底经历气相反应物的交替重复表面反应而在衬底上生长薄膜的各种反应器。 在一个实施方案中,反应器包括反应室。 喷头板将反应室分成上部和下部。 第一前体指向反应室的下半部分,第二前体指向反应室的上半部分。 基板设置在反应室的下半部内。 喷头板包括多个通道,使得上半部分与反应室的下半部连通。 在另一种布置中,反应室的上半部限定了其中形成原位自由基的等离子体腔。 在另一种布置中,反应室包括挡板,其构造成选择性地打开和关闭喷头板中的通道。 在其他布置中,喷头板被布置成改变流过反应室的气体的局部流动模式。
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8.
公开(公告)号:US06727169B1
公开(公告)日:2004-04-27
申请号:US09644416
申请日:2000-08-23
申请人: Ivo Raaijmakers , Suvi P. Haukka , Ville A. Saanila , Pekka J. Soininen , Kai-Erik Elers , Ernst H. A. Granneman
发明人: Ivo Raaijmakers , Suvi P. Haukka , Ville A. Saanila , Pekka J. Soininen , Kai-Erik Elers , Ernst H. A. Granneman
IPC分类号: H01L214763
CPC分类号: C23C16/45525 , C23C16/0272 , C23C16/045 , C23C16/08 , C23C16/14 , C23C16/32 , C23C16/34 , C23C16/44 , C23C16/45534 , C23C16/45536 , C30B25/02 , C30B29/02 , C30B29/36 , H01L21/28562 , H01L21/7681 , H01L21/76814 , H01L21/76843 , H01L21/76846 , H01L21/76873 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53242 , H01L23/53252 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Trenches and contact vias are formed in insulating layers. The trenches and vias are exposed to alternating chemistries to form monolayers of a desired lining material. Exemplary process flows include alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with nitrogen. Near perfect step coverage allows minimal thickness for a diffusion barrier function, thereby maximizing the volume of a subsequent filling metal for any given trench and via dimensions.
摘要翻译: 提供了集成电路中双镶嵌结构的保形衬里的方法和结构。 沟槽和接触通孔形成在绝缘层中。 沟槽和通孔暴露于交替的化学物质以形成所需衬里材料的单层。 示例性工艺流程包括交替脉冲的金属卤化物和注入恒定载流子的氨气。 自身端接的金属层因此与氮气反应。 接近完美的台阶覆盖允许扩散阻挡功能的最小厚度,从而使任何给定沟槽和通孔尺寸的后续填充金属的体积最大化。
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公开(公告)号:US07670944B2
公开(公告)日:2010-03-02
申请号:US11511877
申请日:2006-08-28
申请人: Ivo Raaijmakers , Suvi P. Haukka , Ville A. Saanila , Pekka J. Soininen , Kai-Erik Elers , Ernst H.A. Granneman
发明人: Ivo Raaijmakers , Suvi P. Haukka , Ville A. Saanila , Pekka J. Soininen , Kai-Erik Elers , Ernst H.A. Granneman
IPC分类号: H01L21/4763
CPC分类号: C23C16/45525 , C23C16/0272 , C23C16/045 , C23C16/08 , C23C16/14 , C23C16/32 , C23C16/34 , C23C16/44 , C23C16/45534 , C23C16/45536 , C30B25/02 , C30B29/02 , C30B29/36 , H01L21/28562 , H01L21/7681 , H01L21/76814 , H01L21/76843 , H01L21/76846 , H01L21/76873 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53242 , H01L23/53252 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Trenches and contact vias are formed in insulating layers. The trenches and vias are exposed to alternating chemistries to form monolayers of a desired lining material. Exemplary process flows include alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with nitrogen. Near perfect step coverage allows minimal thickness for a diffusion barrier function, thereby maximizing the volume of a subsequent filling metal for any given trench and via dimensions.
摘要翻译: 提供了集成电路中双镶嵌结构的保形衬里的方法和结构。 沟槽和接触通孔形成在绝缘层中。 沟槽和通孔暴露于交替的化学物质以形成所需衬里材料的单层。 示例性工艺流程包括交替脉冲的金属卤化物和注入恒定载流子的氨气。 自身端接的金属层因此与氮气反应。 接近完美的台阶覆盖允许扩散阻挡功能的最小厚度,从而使任何给定沟槽和通孔尺寸的后续填充金属的体积最大化。
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公开(公告)号:US06780704B1
公开(公告)日:2004-08-24
申请号:US09452844
申请日:1999-12-03
IPC分类号: H01L218242
CPC分类号: H01L28/40 , H01L21/02159 , H01L21/02178 , H01L21/02183 , H01L21/02186 , H01L21/02189 , H01L21/022 , H01L21/0228 , H01L21/02304 , H01L21/31604 , H01L21/3162 , H01L21/31691 , H01L27/10852 , H01L27/10861 , H01L28/84 , Y10T428/265
摘要: Method and structures are provided for conformal capacitor dielectrics over textured silicon electrodes for integrated memory cells. Capacitor structures and first electrodes or plates are formed above or within semiconductor substrates. The first electrodes include hemispherical grain (HSG) silicon for increasing the capacitor plate surface area. The HSG topography is then exposed to alternating chemistries to form monolayers of a desired dielectric material. Exemplary process flows include alternately pulsed metal organic and oxygen source gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with oxygen. Near perfect step coverage allows minimal thickness for a capacitor dielectric, given leakage concerns for particular materials, thereby maximizing the capacitance for the memory cell and increasing cell reliability for a given memory cell design. Alternately pulsed chemistries are also provided for depositing top electrode materials with continuous coverage of capacitor dielectric, realizing the full capacitance benefits of the underlying textured morphology.
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