公开(公告)号：US06358836B1

公开(公告)日：2002-03-19

申请号：US09595823

申请日：2000-06-16

申请人： Szu-Wei Lu ,  Kuo-Chuan Chen ,  Jyh-Rong Lin ,  Ruoh-Huey Wang ,  Hsu-Tien Hu ,  Hsin-Chien Huang

发明人： Szu-Wei Lu ,  Kuo-Chuan Chen ,  Jyh-Rong Lin ,  Ruoh-Huey Wang ,  Hsu-Tien Hu ,  Hsin-Chien Huang

IPC分类号： H01L214763

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00014

摘要： A method for forming a wafer level package by incorporating an insulating pad of an elastic material under a dummy plug is described. In the method, a multiplicity of pads or islands formed of an elastic material is first formed on a pre-processed semiconductor substrate before a multiplicity of dummy via plugs are formed on top. The dummy via plugs are used as a support structure for building I/O redistribution lines (i.e. metal traces) thereon such that I/O bond pads may be built for supporting solder bumps or solder balls. The multiplicity of insulating pads is used for stress relief during a bonding process with the solder ball built on top without the conventional defect of cracking due to high elasticity of the material when a large area insulating layer is deposited on top. Numerous processing advantages are provided by the present invention method which includes the elimination of direct contact between an elastomeric material layer and a polyimide passivation layer such that potential cracking of the polyamide layer or breaking of I/O redistribution lines can be avoided.

摘要翻译： 描述了通过在虚拟插头下方并入弹性材料的绝缘垫来形成晶片级封装的方法。 在该方法中，在多个虚拟通孔插头形成在顶部之前，首先在预处理的半导体衬底上形成由弹性材料形成的多个焊盘或岛。 虚拟通孔插头用作用于在其上构建I / O再分配线（即，金属迹线）的支撑结构，使得可以构建I / O接合焊盘用于支撑焊料凸块或焊球。 绝缘垫的多重性用于在焊接过程中的应力消除，其中，当在顶部沉积大面积的绝缘层时，由于材料的高弹性而不存在常规的破裂缺陷。 通过本发明的方法提供了许多加工优点，其包括消除弹性体材料层和聚酰亚胺钝化层之间的直接接触，从而可以避免聚酰胺层的电位开裂或I / O再分布线断裂。

公开(公告)号：US06605525B2

公开(公告)日：2003-08-12

申请号：US09846643

申请日：2001-05-01

申请人： Szu-Wei Lu ,  Ming Lu ,  Jyh-Rong Lin

发明人： Szu-Wei Lu ,  Ming Lu ,  Jyh-Rong Lin

IPC分类号： H01L2144

CPC分类号： H01L24/12 ,  H01L21/76885 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A method for forming a wafer level package incorporating a multiplicity of elastomeric blocks as stress buffering layer and package formed are described. The method incorporates the step of forming metal lines in-between the plurality of IC dies on a wafer during the same process used for forming the metal vias. The metal lines are subsequently removed by either a mechanical method such as dicing with a diamond saw or by a chemical method such as wet etching. The method allows the fabrications of a wafer level package that has a multiplicity of elastomeric blocks formed on top as stress buffering layer without the CTE mismatch problem with other layers on the wafer.

公开(公告)号：US06277669B1

公开(公告)日：2001-08-21

申请号：US09396060

申请日：1999-09-15

申请人： Ling-Chen Kung ,  Jyh-Rong Lin ,  Kuo-Chuan Chen

发明人： Ling-Chen Kung ,  Jyh-Rong Lin ,  Kuo-Chuan Chen

IPC分类号： H01L2144

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/013

摘要： A method for fabricating a wafer level package and packages formed are disclosed. In the method, an elastomeric material layer is first deposited on top of a passivation layer by a printing, coating or laminating method to form a plurality of isolated islands. The islands may have a thickness of less than 100 &mgr;m. Metal traces for I/O redistribution are then formed to connect the isolated islands with bond pads provided on the surface of the wafer such that one bond pad is connected electrically to one isolated island. On top of the metal trace is then deposited an organic material for insulation with the metal trace on top of the isolated islands exposed. After an UBM layer is formed on top of the metal traces that are exposed on the isolated islands, solder balls of suitable size may be planted by a plating technique, a printing technique or a pick and place technique to complete the wafer level package.

摘要翻译： 公开了一种用于制造晶片级封装和封装形成的方法。 在该方法中，弹性体材料层首先通过印刷，涂覆或层压方法沉积在钝化层的顶部上以形成多个隔离的岛。 这些岛可以具有小于100μm的厚度。 然后形成用于I / O重新分布的金属迹线，以将隔离的岛与提供在晶片表面上的接合焊盘连接，使得一个接合焊盘电连接到一个孤立的岛。 然后在金属痕迹的顶部沉积有机材料，用于绝缘的金属痕迹暴露在孤立岛顶上。 在暴露在孤立岛上的金属迹线的顶部形成UBM层之后，可以通过电镀技术，印刷技术或拾取和放置技术种植合适尺寸的焊球来完成晶片级封装。

公开(公告)号：US07294920B2

公开(公告)日：2007-11-13

申请号：US11186840

申请日：2005-07-22

申请人： Shou-Lung Chen ,  Ching-Wen Hsiao ,  Yu-Hua Chen ,  Jeng-Dar Ko ,  Chih-Ming Tzeng ,  Jyh-Rong Lin ,  Shan-Pu Yu

发明人： Shou-Lung Chen ,  Ching-Wen Hsiao ,  Yu-Hua Chen ,  Jeng-Dar Ko ,  Chih-Ming Tzeng ,  Jyh-Rong Lin ,  Shan-Pu Yu

IPC分类号： H01L23/04

CPC分类号： H01L23/5384 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/351 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/82

摘要： This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.

摘要翻译： 本发明涉及一种晶片级芯片封装方法，包括以下步骤：提供晶片; 将至少一个第一芯片附接到晶片; 在晶片上形成第一绝缘层; 形成穿过所述第一绝缘层的多个第一导电通孔，其中所述第一导电通孔的部分与所述第一芯片电连接; 在所述第一绝缘层的表面上形成导电图案层，其中所述导电图案层与所述第一导电通孔电连接; 形成穿过晶片的多个通孔; 在通孔中填充第二绝缘层; 以及在所述第二绝缘层中形成多个第二导电通孔，其中所述第二导电通孔与所述第一导电通孔电连接。

公开(公告)号：US20060157864A1

公开(公告)日：2006-07-20

申请号：US11269613

申请日：2005-11-09

申请人： Shou-Lung Chen ,  Ching-Wen Hsiao ,  Yu-Hua Chen ,  Jeng-Dar Ko ,  Jyh-Rong Lin

发明人： Shou-Lung Chen ,  Ching-Wen Hsiao ,  Yu-Hua Chen ,  Jeng-Dar Ko ,  Jyh-Rong Lin

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L24/97 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2224/82

摘要： The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are disclosed. The method comprises: providing a substrate having a plurality of vias and a plurality of electronic devices; forming a gluing layer on a surface of the substrate and fixing the electronic devices on the gluing layer, wherein the electronic devices have I/O units aligned with the vias respectively; forming a plurality of fixing layers in the gaps between the electronic devices; trenching a plurality of openings aligned with the vias respectively in the fixing layer; forming a plurality of metallic conductive units in the vias, the openings and part of the surface of the substrate; and forming a passivation layer over the other surface of the substrate.

公开(公告)号：US08587091B2

公开(公告)日：2013-11-19

申请号：US13533251

申请日：2012-06-26

申请人： Shou-Lung Chen ,  Ching-Wen Hsiao ,  Yu-Hua Chen ,  Jeng-Dar Ko ,  Chih-Ming Tzeng ,  Jyh-Rong Lin ,  Shan-Pu Yu

发明人： Shou-Lung Chen ,  Ching-Wen Hsiao ,  Yu-Hua Chen ,  Jeng-Dar Ko ,  Chih-Ming Tzeng ,  Jyh-Rong Lin ,  Shan-Pu Yu

IPC分类号： H01L21/4763

CPC分类号： H01L23/5384 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/351 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/82

摘要： A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.

摘要翻译： 一种晶片级芯片封装方法，包括以下步骤：提供晶片; 将至少一个第一芯片附接到晶片; 在晶片上形成第一绝缘层; 形成穿过所述第一绝缘层的多个第一导电通孔，其中所述第一导电通孔的部分与所述第一芯片电连接; 在所述第一绝缘层的表面上形成导电图案层，其中所述导电图案层与所述第一导电通孔电连接; 形成穿过晶片的多个通孔; 在通孔中填充第二绝缘层; 以及在所述第二绝缘层中形成多个第二导电通孔，其中所述第二导电通孔与所述第一导电通孔电连接。

公开(公告)号：US08248803B2

公开(公告)日：2012-08-21

申请号：US12751741

申请日：2010-03-31

申请人： Jyh-Rong Lin ,  Ming Lu

发明人： Jyh-Rong Lin ,  Ming Lu

IPC分类号： H05K7/20

CPC分类号： H01L23/3677 ,  H01L33/641 ,  H01L33/642 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： The subject invention relates to a semiconductor package and method of manufacturing the same. The semiconductor package of the subject invention comprises a substrate with a through hole penetrating therethrough; a semiconductor chip positioned on the substrate covering the through hole; and a thermal conductive device filling the through hole and contacting the semiconductor chip. According to the subject invention, the thermal resistance in the structure of the semiconductor package is substantially reduced and thus desirable performance of heat spreading or dissipation is achieved. In addition, the production cost and size of the semiconductor package are also reduced.

摘要翻译： 本发明涉及一种半导体封装及其制造方法。 本发明的半导体封装包括具有穿透其中的通孔的基板; 位于所述基板上的覆盖所述通孔的半导体芯片; 以及填充所述通孔并接触所述半导体芯片的导热装置。 根据本发明，半导体封装的结构中的热阻大大降低，从而实现了热扩散或散热所需的性能。 此外，半导体封装的制造成本和尺寸也降低。

公开(公告)号：US07632707B2

公开(公告)日：2009-12-15

申请号：US11269613

申请日：2005-11-09

申请人： Shou-Lung Chen ,  Ching-Wen Hsiao ,  Yu-Hua Chen ,  Jeng-Dar Ko ,  Jyh-Rong Lin

发明人： Shou-Lung Chen ,  Ching-Wen Hsiao ,  Yu-Hua Chen ,  Jeng-Dar Ko ,  Jyh-Rong Lin

IPC分类号： H01L21/00

CPC分类号： H01L24/97 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2224/82

摘要： The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are disclosed. The method comprises: providing a substrate having a plurality of vias and a plurality of electronic devices; forming a gluing layer on a surface of the substrate and fixing the electronic devices on the gluing layer, wherein the electronic devices have I/O units aligned with the vias respectively; forming a plurality of fixing layers in the gaps between the electronic devices; trenching a plurality of openings aligned with the vias respectively in the fixing layer; forming a plurality of metallic conductive units in the vias, the openings and part of the surface of the substrate; and forming a passivation layer over the other surface of the substrate.

摘要翻译： 本发明公开了一种电子装置封装和封装方法。 具体地，公开了一种适用于具有增强的电气性能和散热效率的无扰动电子器件封装的封装的电子器件封装和方法。 该方法包括：提供具有多个通孔和多个电子器件的衬底; 在所述基板的表面上形成胶合层并将所述电子装置固定在所述胶合层上，其中所述电子装置具有分别与所述通孔对准的I / O单元; 在电子设备之间的间隙中形成多个固定层; 在固定层中分别与通孔对准的多个开口挖沟; 在通孔，开口和基板的表面的一部分上形成多个金属导电单元; 以及在所述衬底的另一表面上形成钝化层。

公开(公告)号：US07411306B2

公开(公告)日：2008-08-12

申请号：US11194669

申请日：2005-08-02

申请人： Fang-Jun Leu ,  Shou-Lung Chen ,  Ching-Wen Hsiao ,  Shan-Pu Yu ,  Jyh-Rong Lin ,  I-Hsuan Peng ,  Jian-Shu Wu ,  Hui-Mei Wu ,  Chien-Wei Chieh

发明人： Fang-Jun Leu ,  Shou-Lung Chen ,  Ching-Wen Hsiao ,  Shan-Pu Yu ,  Jyh-Rong Lin ,  I-Hsuan Peng ,  Jian-Shu Wu ,  Hui-Mei Wu ,  Chien-Wei Chieh

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L31/0203 ,  H01L27/14618 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/07811 ,  H01L2924/15321 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/0401

摘要： This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active area and at least one passive chip on the transparent substrate, wherein the photosensitive active area faces the transparent substrate; forming an insulating build-up film over the transparent substrate; and forming a plurality of conductive vias in the insulating build-up film wherein the ends of the conductive vias are connected with the passive chip or the first patterned conductive layer of the transparent substrate while the other ends of the conductive vias are exposed on the surface of the insulating build-up film. The packaging method is capable of down-sizing the construction of the image sensor module and simplifying the processing steps.

摘要翻译： 本发明涉及图像传感器模块的封装结构和方法。 该方法包括：提供具有第一图案化导电层的透明基板; 在所述透明基板上承载具有感光有源区域的图像传感器集成电路芯片和至少一个无源芯片，其中所述光敏有源区域面向所述透明基板; 在透明基板上形成绝缘堆积膜; 并且在绝缘堆积膜中形成多个导电通孔，其中导电通孔的端部与透明基板的无源芯片或第一图案化导电层连接，而导电通孔的另一端暴露在表面上 的绝缘堆积膜。 包装方法能够缩小图像传感器模块的结构，简化了处理步骤。

公开(公告)号：US20060030070A1

公开(公告)日：2006-02-09

申请号：US11194669

申请日：2005-08-02

申请人： Fang-Jun Leu ,  Shou-Lung Chen ,  Ching-Wen Hsiao ,  Shan-Pu Yu ,  Jyh-Rong Lin ,  I-Hsuan Peng ,  Jian-Shu Wu ,  Hui-Mei Wu ,  Chien-Wei Chieh

发明人： Fang-Jun Leu ,  Shou-Lung Chen ,  Ching-Wen Hsiao ,  Shan-Pu Yu ,  Jyh-Rong Lin ,  I-Hsuan Peng ,  Jian-Shu Wu ,  Hui-Mei Wu ,  Chien-Wei Chieh

IPC分类号： H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC分类号： H01L31/0203 ,  H01L27/14618 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/07811 ,  H01L2924/15321 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/0401

摘要： This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active area and at least one passive chip on the transparent substrate, wherein the photosensitive active area faces the transparent substrate; forming an insulating build-up film over the transparent substrate; and forming a plurality of conductive vias in the insulating build-up film wherein the ends of the conductive vias are connected with the passive chip or the first patterned conductive layer of the transparent substrate while the other ends of the conductive vias are exposed on the surface of the insulating build-up film. The packaging method is capable of down-sizing the construction of the image sensor module and simplifying the processing steps.