公开(公告)号：US3900944A

公开(公告)日：1975-08-26

申请号：US42638473

申请日：1973-12-19

Applicant: TEXAS INSTRUMENTS INC

Inventor： FULLER CLYDE R ,  REINBERG ALAN R

IPC: H01L21/00 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/532 ,  H01L21/283 ,  H01L21/308 ,  H01L21/312

CPC classification number: H01L23/53252 ,  H01L21/00 ,  H01L21/32134 ,  H01L21/32136 ,  H01L23/522 ,  H01L23/53242 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved method of forming interconnections on a semiconductor slice in which a barrier metal of TI:W or Ta is deposited followed by deposit of a conducting layer and then a masking layer of Ta after which the masking layer is patterned with photo-resist and plasma etched whereupon the conducting layer is sputter etched with the barrier layer then being removed to provide an interconnecting lead with sloping sides over which insulation and a second level of metallization may be applied without danger of problems at crossovers.

Abstract translation: 一种在半导体薄片上形成互连的改进方法，其中沉积TI：W或Ta的势垒金属，然后沉积导电层，然后沉积Ta的掩蔽层，之后用光刻胶和等离子体对掩模层进行图案化 蚀刻，然后用阻挡层溅射蚀刻导电层，然后被去除，以提供互连引线与倾斜的侧面，绝缘和第二级别的金属化可以在其上施加，而不会在交叉上出现问题。

公开(公告)号：US3617818A

公开(公告)日：1971-11-02

申请号：US3617818D

申请日：1968-12-31

Applicant: TEXAS INSTRUMENTS INC

Inventor： FULLER CLYDE R

IPC: H01L21/00 ,  H01L21/60 ,  H01L23/485 ,  H01L3/00 ,  H01L5/00

CPC classification number: H01L24/85 ,  H01L21/00 ,  H01L23/485 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02126 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05555 ,  H01L2224/05624 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/78301 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  Y10S428/929 ,  Y10T428/12528 ,  Y10T428/12639 ,  Y10T428/12833 ,  Y10T428/12847 ,  H01L2224/78 ,  H01L2924/00

Abstract: A gold-bonding area is exposed by an opening in the upper molybdenum layer of a trimetal molybdenum-gold-molybdenum contact system for a semiconductor device. A layer of chromium, or other suitable corrosion-resistant material, is formed over the edges of the molybdenum layers and extends for a distance over the exposed gold-bonding area in order to seal the edges of the molybdenum layers. An insulation layer is formed over the layer of chromium and selectively removed to define an opening exposing the gold-bonding area. In one embodiment, a second layer of gold is formed over the edges of the chromium layer, with the insulation layer abutting the outer edges of the second gold layer.

公开(公告)号：US3657029A

公开(公告)日：1972-04-18

申请号：US78818768

申请日：1968-12-31

Applicant: TEXAS INSTRUMENTS INC

Inventor： FULLER CLYDE R

IPC: C23F1/02 ,  H01L21/00 ,  B44D1/18 ,  C23B5/64

CPC classification number: C23F1/02 ,  H01L21/00

Abstract: Platinum thin-film metallization is selectively etched with aqua regia, using a chromium or titanium film as an etch-resistant mask. In a specific embodiment, an integrated circuit structure is metallized with successive layers of titanium, platinum, gold and a metal selected from molybdenum, tungsten, rhenium and corrosion-resistant alloys thereof. The system is particularly suited for the formation of insulated ''''cross-over'''' metallization, or multi-level interconnecting metallization.

Abstract translation: 使用铬或钛膜作为耐蚀刻掩模，用王水选择性地蚀刻铂薄膜金属化。 在具体实施例中，集成电路结构用钛，铂，金和选自钼，钨，铼的金属和其耐腐蚀合金的连续层进行金属化。 该系统特别适用于形成绝缘的“交叉”金属化或多层互连金属化。

公开(公告)号：US3573570A

公开(公告)日：1971-04-06

申请号：US3573570D

申请日：1970-02-26

Applicant: TEXAS INSTRUMENTS INC

Inventor： FULLER CLYDE R ,  CUNNINGHAM JAMES A

IPC: H01L21/00 ,  H01L23/485 ,  H01L23/522 ,  H01L3/00 ,  H01L5/00

CPC classification number: H01L23/485 ,  H01L21/00 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a tungsten ohmic contact and electrical interconnection system for semiconductor devices. Particularly, a system of one or more levels of multilayer metal interconnections for integrated circuits. The multilayer metal interconnections are composed of outer tungsten layers of metal that adhere well to silicon and silicon oxide with an intermediate layer of high conductivity metal. Different levels of multilayer metal interconnections are separated from one another by insulating layers with holes that allow ohmic contacts to be made between different levels. The final or top multilayer metal interconnections can have one adherent metal layer covered by the high conductive metal layer.

公开(公告)号：US3654526A

公开(公告)日：1972-04-04

申请号：US3654526D

申请日：1970-05-19

Applicant: TEXAS INSTRUMENTS INC

Inventor： CUNNINGHAM JAMES A ,  FULLER CLYDE R ,  HOOPER ROBERT C ,  WAKEFIELD ROBERT H

IPC: H01L21/00 ,  H01L23/482 ,  H01L23/522 ,  H01L23/532 ,  H01L5/02

CPC classification number: H01L23/53295 ,  H01L21/00 ,  H01L23/4822 ,  H01L23/522 ,  H01L23/5329 ,  H01L24/01 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/00

Abstract: A metallization system for semiconductor devices includes a first layer of aluminum a part of which is in ohmic contact with a silicon substrate and devices thereon, the other part of which overlies an insulating layer. A second layer of molybdenum is deposited on the aluminum layer. The aluminum and molybdenum are photoetched into a predetermined pattern which ohmically contacts the silicon and overlies an insulating layer, usually of silicon dioxide. Thereafter a variety of techniques and lead systems can be used. For example, a second layer of insulating material can be applied over the first level aluminum-molybdenum metallization system and the first layer of insulating material. The second level of insulating material can then be selectively etched to expose predetermined portions of the first level lead system. Thereafter, beam leads can be attached to the first level metallization system; or bonding pads can be formed in ohmic contact with the first level metallization system. Alternatively, a second level metallization system can be utilized where it becomes necessary to conductively connect various components on the semiconductor device by lead cross-overs. A third layer of insulating material can then be applied on top of the second level metallization system. After selective etching of the second level insulating material, beam leads, bonding pads or even a third level metallization system can be applied.

Abstract translation: 用于半导体器件的金属化系统包括第一层铝，其一部分与硅衬底和其上的器件欧姆接触，其另一部分覆盖绝缘层。 第二层钼沉积在铝层上。 铝和钼被光刻成预定的图案，其与硅接触并覆盖绝缘层，通常为二氧化硅。 此后可以使用各种技术和引导系统。 例如，可以在第一级铝 - 钼金属化系统和第一绝缘材料层上施加第二层绝缘材料。 然后可以选择性地蚀刻第二级绝缘材料以暴露第一级引线系统的预定部分。 此后，光束引线可以附接到第一级金属化系统; 或者接合焊盘可以与第一级金属化系统欧姆接触形成。 或者，可以利用第二级金属化系统，其中需要通过引线交叉导电地连接半导体器件上的各种部件。 然后可以将第三层绝缘材料施加在第二层金属化系统的顶部上。 在选择性地蚀刻第二级绝缘材料之后，可以应用光束引线，焊盘或甚至第三级金属化系统。

公开(公告)号：US3632438A

公开(公告)日：1972-01-04

申请号：US3632438D

申请日：1967-09-29

Applicant: TEXAS INSTRUMENTS INC

Inventor： CARLSON HAROLD G ,  FULLER CLYDE R ,  BROWN GEORGE A

IPC: H01L23/29 ,  H01L29/00 ,  C23C13/04

CPC classification number: H01L23/29 ,  H01L29/00 ,  H01L2224/48463 ,  H01L2224/4918 ,  H01L2924/1305 ,  H01L2924/13091 ,  Y10S148/017 ,  Y10S148/043 ,  Y10S148/051 ,  Y10S148/053 ,  Y10S148/06 ,  Y10S148/118 ,  Y10S148/122 ,  H01L2924/00

Abstract: Disclosed is a method of forming an insulating layer having an unusually low concentration of contaminating impurities such as sodium, copper, and iron on the surface of a semiconductor substrate during device fabrication. After the insulating layer has been grown or deposited on the surface of the substrate, a thin surface portion of the layer is removed by etching to a depth sufficient to remove a major portion of the impurities present in the layer. In one embodiment a glass film is formed on the surface of the layer by a reaction between an impurity modifier and the layer during processing of the device, to cause the impurities to concentrate in the glass film, and the glass film is removed, removing a major portion of the impurity contamination present in the layer. As a precaution against further contamination, a layer of barrier material is formed on the insulating layer.

Abstract translation: 公开了在器件制造期间在半导体衬底的表面上形成具有异常低浓度的污染杂质如钠，铜和铁的绝缘层的方法。 在绝缘层已经生长或沉积在衬底的表面上之后，通过蚀刻去除该层的薄表面部分到足以去除存在于该层中的大部分杂质的深度。 在一个实施方案中，通过在器件加工期间杂质改性剂与该层之间的反应在该层的表面上形成玻璃膜，以使杂质浓缩在玻璃膜中，并除去玻璃膜 杂质污染物的主要部分存在于该层中。 作为防止进一步污染的预防措施，在绝缘层上形成阻挡材料层。

公开(公告)号：US3647663A

公开(公告)日：1972-03-07

申请号：US3647663D

申请日：1968-01-19

Applicant: TEXAS INSTRUMENTS INC

Inventor： CUNNINGHAM JAMES A ,  FULLER CLYDE R ,  WOOD SAMUEL J JR

IPC: H01L21/00 ,  H01L23/29 ,  H01L23/522 ,  C23C15/00

CPC classification number: H01L23/291 ,  H01L21/00 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: DISCLOSED IS A METHOD OF FORMING A COMPOSITE INSULATING LAYER FOR USE, PRIMARILY, IN MULTILEVEL INTEGRATED CIRCUITS. AN RF-SPUTTERED SILICON OXIDE LAYER IS DEPOSITED OVER THE FIRST LAYER CONTACTS OF A MONOCRYSTALLINE INTEGRATED CIRCUILT FOLLOWED BY THE DEPOSITION OF A LAYER OF OXIDATIVE SILICON OXIDE RESULTING FROM A REACTION OF SILANE SIH4 WITH OXYGEN 02 TO FORM A COMPOSITE INSULATING LAYER. THE COMPOSITE INSULATING LAYER COMBINES THE ADVANTAGE OF THE SILICON OXIDE LAYER FORMED BY EITHER METHOD BUT WITH MORE OF THE DISADVANTAGES INHERENT IN EITHER.

公开(公告)号：US3290180A

公开(公告)日：1966-12-06

申请号：US44576765

申请日：1965-04-05

Applicant: TEXAS INSTRUMENTS INC

Inventor： BAIRD STEPHEN S ,  FULLER CLYDE R

IPC: H01L21/306 ,  H01L21/316 ,  H01L23/29

CPC classification number: H01L21/02052 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02307 ,  H01L21/31662 ,  H01L23/293 ,  H01L2924/0002 ,  Y10S148/003 ,  Y10S148/017 ,  Y10S148/118 ,  Y10S438/906 ,  H01L2924/00