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公开(公告)号：US10157849B2
公开(公告)日：2018-12-18
申请号：US15443490
申请日：2017-02-27
Inventor： Chih-Fan Huang , Cheng-Tar Wu , Ming-Da Cheng , Chung-Shi Liu , Chen-Hua Yu
IPC: H01L23/538 , H01L21/56 , H01L21/48 , H01L25/10 , H01L23/29 , H01L23/00 , H01L25/00 , H01L23/498 , H01L23/31
Abstract: A method includes molding a device die in a molding material, wherein a metal pillar of the device die is exposed through a surface of the molding material. A substrate is adhered to the molding material. The substrate includes a redistribution layer that further includes redistribution lines. A plating is performed to fill a through-opening in the substrate to form a through-via. The through-via is plated on the metal pillar of the device die. An electrical connector is formed to electrically couple to the through-via.
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Patent Agency Ranking
公开(公告)号：US20160035666A1
公开(公告)日：2016-02-04
申请号：US14446583
申请日：2014-07-30
Inventor： Chih-Fan Huang , Cheng-Tar Wu , Ming-Da Cheng , Chung-Shi Liu , Chen-Hua Yu
IPC: H01L23/498 , H01L21/48 , H01L21/56
CPC classification number: H01L23/5389 , H01L21/481 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/565 , H01L23/295 , H01L23/3114 , H01L23/3121 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L24/19 , H01L24/20 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/18 , H01L2224/19 , H01L2224/24137 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/18162 , H01L2224/83 , H01L2924/00012 , H01L2924/00014 , H01L2924/00 , H01L2224/83005
Abstract: A method includes molding a device die in a molding material, wherein a metal pillar of the device die is exposed through a surface of the molding material. A substrate is adhered to the molding material. The substrate includes a redistribution layer that further includes redistribution lines. A plating is performed to fill a through-opening in the substrate to form a through-via. The through-via is plated on the metal pillar of the device die. An electrical connector is formed to electrically couple to the through-via.
Abstract translation: 一种方法包括在模制材料中模制器件模具，其中器件裸片的金属柱通过模制材料的表面暴露。 将基材粘合到成型材料上。 衬底包括还包括再分布线的再分布层。 进行电镀以填充衬底中的通孔以形成通孔。 通孔被电镀在器件裸片的金属柱上。 电连接器形成为电耦合到通孔。
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公开(公告)号：US20170154811A1
公开(公告)日：2017-06-01
申请号：US14953783
申请日：2015-11-30
Inventor： Cheng-Tar Wu , Chung-Shi Liu , Chih-Wei Lin , Hui-Min Huang , Chun-Cheng Lin , Ming-Da Cheng
IPC: H01L21/768 , H01L23/00 , H01L23/532
CPC classification number: H01L21/76834 , H01L21/56 , H01L21/76828 , H01L23/291 , H01L23/295 , H01L23/3114 , H01L23/3192 , H01L23/5328 , H01L23/5329 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L2224/02313 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05164 , H01L2224/05181 , H01L2224/05548 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2224/10125 , H01L2224/10126 , H01L2224/11462 , H01L2224/1191 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13184 , H01L2924/00014 , H01L2924/014
Abstract: A method of forming a wafer level chip scale package interconnect may include: forming a post-passivation interconnect (PPI) layer over a substrate; forming an interconnect over the PPI layer; and releasing a molding compound material over the substrate, the molding compound material flowing to laterally encapsulate a portion of the interconnect.
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公开(公告)号：US09601353B2
公开(公告)日：2017-03-21
申请号：US14446583
申请日：2014-07-30
Inventor： Chih-Fan Huang , Cheng-Tar Wu , Ming-Da Cheng , Chung-Shi Liu , Chen-Hua Yu
IPC: H01L21/00 , H01L21/48 , H01L21/56 , H01L25/10 , H01L23/498 , H01L23/538
CPC classification number: H01L23/5389 , H01L21/481 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/565 , H01L23/295 , H01L23/3114 , H01L23/3121 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L24/19 , H01L24/20 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/18 , H01L2224/19 , H01L2224/24137 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/18162 , H01L2224/83 , H01L2924/00012 , H01L2924/00014 , H01L2924/00 , H01L2224/83005
Abstract: A method includes molding a device die in a molding material, wherein a metal pillar of the device die is exposed through a surface of the molding material. A substrate is adhered to the molding material. The substrate includes a redistribution layer that further includes redistribution lines. A plating is performed to fill a through-opening in the substrate to form a through-via. The through-via is plated on the metal pillar of the device die. An electrical connector is formed to electrically couple to the through-via.
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公开(公告)号：US09892962B2
公开(公告)日：2018-02-13
申请号：US14953783
申请日：2015-11-30
Inventor： Cheng-Tar Wu , Chung-Shi Liu , Chih-Wei Lin , Hui-Min Huang , Chun-Cheng Lin , Ming-Da Cheng
IPC: H01L21/768 , H01L23/532 , H01L23/00
CPC classification number: H01L21/76834 , H01L21/56 , H01L21/76828 , H01L23/291 , H01L23/295 , H01L23/3114 , H01L23/3192 , H01L23/5328 , H01L23/5329 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L2224/02313 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05164 , H01L2224/05181 , H01L2224/05548 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2224/10125 , H01L2224/10126 , H01L2224/11462 , H01L2224/1191 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13184 , H01L2924/00014 , H01L2924/014
Abstract: A method of forming a wafer level chip scale package interconnect may include: forming a post-passivation interconnect (PPI) layer over a substrate; forming an interconnect over the PPI layer; and releasing a molding compound material over the substrate, the molding compound material flowing to laterally encapsulate a portion of the interconnect.
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公开(公告)号：US20170170124A1
公开(公告)日：2017-06-15
申请号：US15443490
申请日：2017-02-27
Inventor： Chih-Fan Huang , Cheng-Tar Wu , Ming-Da Cheng , Chung-Shi Liu , Chen-Hua Yu
CPC classification number: H01L23/5389 , H01L21/481 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/565 , H01L23/295 , H01L23/3114 , H01L23/3121 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L24/19 , H01L24/20 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/18 , H01L2224/19 , H01L2224/24137 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/18162 , H01L2224/83 , H01L2924/00012 , H01L2924/00014 , H01L2924/00 , H01L2224/83005
Abstract: A method includes molding a device die in a molding material, wherein a metal pillar of the device die is exposed through a surface of the molding material. A substrate is adhered to the molding material. The substrate includes a redistribution layer that further includes redistribution lines. A plating is performed to fill a through-opening in the substrate to form a through-via. The through-via is plated on the metal pillar of the device die. An electrical connector is formed to electrically couple to the through-via.
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