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公开(公告)号：US10032698B2
公开(公告)日：2018-07-24
申请号：US15614339
申请日：2017-06-05
发明人： Hsiao Yun Lo , Yung-Chi Lin , Yang-Chih Hsueh , Tsang-Jiuh Wu , Wen-Chih Chiou
IPC分类号： H01L23/48 , H01L23/50 , H01L21/44 , H01L21/768 , H01L23/532 , H01L23/00 , H01L21/288 , H01L23/525
摘要： An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.
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公开(公告)号：US20180145046A1
公开(公告)日：2018-05-24
申请号：US15863240
申请日：2018-01-05
发明人： Hsiao Yun Lo , Lin-Chih Huang , Tasi-Jung Wu , Hsin-Yu Chen , Yung-Chi Lin , Ku-Feng Yang , Tsang-Jiuh Wu , Wen-Chih Chiou
IPC分类号： H01L23/00
摘要： A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.
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公开(公告)号：US09679859B2
公开(公告)日：2017-06-13
申请号：US14991560
申请日：2016-01-08
发明人： Hsiao Yun Lo , Lin-Chih Huang , Tasi-Jung Wu , Hsin-Yu Chen , Yung-Chi Lin , Ku-Feng Yang , Tsang-Jiuh Wu , Wen-Chih Chiou
CPC分类号： H01L24/05 , H01L23/481 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/0346 , H01L2224/03462 , H01L2224/03602 , H01L2224/03614 , H01L2224/03616 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05012 , H01L2224/05017 , H01L2224/05025 , H01L2224/05026 , H01L2224/05082 , H01L2224/05083 , H01L2224/05124 , H01L2224/05139 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05187 , H01L2224/05565 , H01L2224/05571 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/05684 , H01L2224/11334 , H01L2224/1145 , H01L2224/11462 , H01L2224/13023 , H01L2224/13026 , H01L2224/131 , H01L2224/13111 , H01L2224/13147 , H01L2924/00012 , H01L2924/00014 , H01L2924/01029 , H01L2924/01047 , H01L2924/013 , H01L2924/13091 , H01L2924/04941 , H01L2924/04953 , H01L2924/014
摘要： An apparatus comprises a dielectric layer formed on a first side of a substrate, a first side interconnect structure comprising a first metal line and a pad formed in the dielectric layer, wherein the pad comprises a bottom portion formed of a first conductive metal and an upper portion formed of a second conductive metal, and wherein sidewalls of the upper portion are surrounded by the bottom portion and a top surface of the pad is coplanar with a top surface of the first metal line and a passivation layer formed over the dielectric layer.
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公开(公告)号：US09252110B2
公开(公告)日：2016-02-02
申请号：US14158364
申请日：2014-01-17
发明人： Hsiao Yun Lo , Lin-Chih Huang , Tasi-Jung Wu , Hsin-Yu Chen , Yung-Chi Lin , Ku-Feng Yang , Tsang-Jiuh Wu , Wen-Chih Chiou
IPC分类号： H01L21/4763 , H01L23/00
CPC分类号： H01L24/05 , H01L23/481 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/0346 , H01L2224/03462 , H01L2224/03602 , H01L2224/03614 , H01L2224/03616 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05012 , H01L2224/05017 , H01L2224/05025 , H01L2224/05026 , H01L2224/05082 , H01L2224/05083 , H01L2224/05124 , H01L2224/05139 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05187 , H01L2224/05565 , H01L2224/05571 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/05684 , H01L2224/11334 , H01L2224/1145 , H01L2224/11462 , H01L2224/13023 , H01L2224/13026 , H01L2224/131 , H01L2224/13111 , H01L2224/13147 , H01L2924/00012 , H01L2924/00014 , H01L2924/01029 , H01L2924/01047 , H01L2924/013 , H01L2924/13091 , H01L2924/04941 , H01L2924/04953 , H01L2924/014
摘要： An apparatus comprises a dielectric layer formed on a first side of a substrate, a first side interconnect structure comprising a first metal line and a pad formed in the dielectric layer, wherein the pad comprises a bottom portion formed of a first conductive metal and an upper portion formed of a second conductive metal, and wherein sidewalls of the upper portion are surrounded by the bottom portion and a top surface of the pad is coplanar with a top surface of the first metal line and a passivation layer formed over the dielectric layer, wherein the first metal line is embedded in the passivation layer.
摘要翻译： 一种装置包括形成在基板的第一侧上的电介质层，第一侧互连结构，包括第一金属线和形成在电介质层中的焊盘，其中该焊盘包括由第一导电金属和上部 部分由第二导电金属形成，并且其中上部的侧壁由底部包围，并且焊盘的顶表面与第一金属线的顶表面和形成在电介质层上的钝化层共面，其中 第一金属线嵌入在钝化层中。
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公开(公告)号：US20170271287A1
公开(公告)日：2017-09-21
申请号：US15613579
申请日：2017-06-05
发明人： Hsiao Yun Lo , Lin-Chih Huang , Tasi-Jung Wu , Hsin-Yu Chen , Yung-Chi Lin , Ku-Feng Yang , Tsang-Jiuh Wu , Wen-Chih Chiou
IPC分类号： H01L23/00
CPC分类号： H01L24/05 , H01L23/481 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/0346 , H01L2224/03462 , H01L2224/03602 , H01L2224/03614 , H01L2224/03616 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05012 , H01L2224/05017 , H01L2224/05025 , H01L2224/05026 , H01L2224/05082 , H01L2224/05083 , H01L2224/05124 , H01L2224/05139 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05187 , H01L2224/05565 , H01L2224/05571 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/05684 , H01L2224/11334 , H01L2224/1145 , H01L2224/11462 , H01L2224/13023 , H01L2224/13026 , H01L2224/131 , H01L2224/13111 , H01L2224/13147 , H01L2924/00012 , H01L2924/00014 , H01L2924/01029 , H01L2924/01047 , H01L2924/013 , H01L2924/13091 , H01L2924/04941 , H01L2924/04953 , H01L2924/014
摘要： A method includes depositing a dielectric layer over a substrate, patterning the dielectric layer to form a first opening and a second opening, wherein a width of the second opening is greater than a width of the first opening, forming a first metal layer over the dielectric layer, wherein a planar surface of the first metal layer in the second opening is lower than a top surface of the dielectric layer, forming a second metal layer in a conformal manner over the first metal layer, wherein a material of the first metal layer is different from a material of the second metal layer and applying a polishing process to the first metal layer and the second metal layer until the dielectric layer is exposed.
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公开(公告)号：US20160118356A1
公开(公告)日：2016-04-28
申请号：US14991560
申请日：2016-01-08
发明人： Hsiao Yun Lo , Lin-Chih Huang , Tasi-Jung Wu , Hsin-Yu Chen , Yung-Chi Lin , Ku-Feng Yang , Tsang-Jiuh Wu , Wen-Chih Chiou
IPC分类号： H01L23/00
CPC分类号： H01L24/05 , H01L23/481 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/0346 , H01L2224/03462 , H01L2224/03602 , H01L2224/03614 , H01L2224/03616 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05012 , H01L2224/05017 , H01L2224/05025 , H01L2224/05026 , H01L2224/05082 , H01L2224/05083 , H01L2224/05124 , H01L2224/05139 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05187 , H01L2224/05565 , H01L2224/05571 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/05684 , H01L2224/11334 , H01L2224/1145 , H01L2224/11462 , H01L2224/13023 , H01L2224/13026 , H01L2224/131 , H01L2224/13111 , H01L2224/13147 , H01L2924/00012 , H01L2924/00014 , H01L2924/01029 , H01L2924/01047 , H01L2924/013 , H01L2924/13091 , H01L2924/04941 , H01L2924/04953 , H01L2924/014
摘要： An apparatus comprises a dielectric layer formed on a first side of a substrate, a first side interconnect structure comprising a first metal line and a pad formed in the dielectric layer, wherein the pad comprises a bottom portion formed of a first conductive metal and an upper portion formed of a second conductive metal, and wherein sidewalls of the upper portion are surrounded by the bottom portion and a top surface of the pad is coplanar with a top surface of the first metal line and a passivation layer formed over the dielectric layer.
摘要翻译： 一种装置包括形成在基板的第一侧上的电介质层，第一侧互连结构，包括第一金属线和形成在电介质层中的焊盘，其中该焊盘包括由第一导电金属和上部 部分由第二导电金属形成，并且其中上部的侧壁被底部部分包围，并且焊盘的顶表面与第一金属线的顶表面和形成在电介质层上的钝化层共面。
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公开(公告)号：US10811374B2
公开(公告)日：2020-10-20
申请号：US15863240
申请日：2018-01-05
发明人： Hsiao Yun Lo , Lin-Chih Huang , Tasi-Jung Wu , Hsin-Yu Chen , Yung-Chi Lin , Ku-Feng Yang , Tsang-Jiuh Wu , Wen-Chih Chiou
摘要： A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.
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公开(公告)号：US10157866B2
公开(公告)日：2018-12-18
申请号：US15613579
申请日：2017-06-05
发明人： Hsiao Yun Lo , Lin-Chih Huang , Tasi-Jung Wu , Hsin-Yu Chen , Yung-Chi Lin , Ku-Feng Yang , Tsang-Jiuh Wu , Wen-Chih Chiou
摘要： A method includes depositing a dielectric layer over a substrate, patterning the dielectric layer to form a first opening and a second opening, wherein a width of the second opening is greater than a width of the first opening, forming a first metal layer over the dielectric layer, wherein a planar surface of the first metal layer in the second opening is lower than a top surface of the dielectric layer, forming a second metal layer in a conformal manner over the first metal layer, wherein a material of the first metal layer is different from a material of the second metal layer and applying a polishing process to the first metal layer and the second metal layer until the dielectric layer is exposed.
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公开(公告)号：US20170271242A1
公开(公告)日：2017-09-21
申请号：US15614339
申请日：2017-06-05
发明人： Hsiao Yun Lo , Yung-Chi Lin , Yang-Chih Hsueh , Tsang-Jiuh Wu , Wen-Chih Chiou
IPC分类号： H01L23/48 , H01L21/768 , H01L23/00 , H01L23/532 , H01L21/288 , H01L23/525
CPC分类号： H01L23/481 , H01L21/2885 , H01L21/76847 , H01L21/7685 , H01L21/76885 , H01L21/76898 , H01L23/525 , H01L23/53214 , H01L23/53228 , H01L23/53242 , H01L24/03 , H01L24/05 , H01L24/13 , H01L29/43 , H01L2224/0345 , H01L2224/03462 , H01L2224/0347 , H01L2224/03616 , H01L2224/0391 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05005 , H01L2224/05018 , H01L2224/05023 , H01L2224/05025 , H01L2224/05026 , H01L2224/05099 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/05164 , H01L2224/05166 , H01L2224/0518 , H01L2224/05181 , H01L2224/05184 , H01L2224/05541 , H01L2224/05552 , H01L2224/05567 , H01L2224/05568 , H01L2224/0557 , H01L2224/05571 , H01L2224/0558 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/0568 , H01L2224/05681 , H01L2224/1131 , H01L2224/1134 , H01L2224/11849 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2924/00 , H01L2924/00011 , H01L2924/00012 , H01L2924/00014 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H01L2924/207
摘要： An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.
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公开(公告)号：US09673132B2
公开(公告)日：2017-06-06
申请号：US14511006
申请日：2014-10-09
发明人： Hsiao Yun Lo , Yung-Chi Lin , Yang-Chih Hsueh , Tsang-Jiuh Wu , Wen-Chih Chiou
IPC分类号： H01L23/48 , H01L21/768 , H01L23/00 , H01L23/532 , H01L21/288 , H01L23/525
CPC分类号： H01L23/481 , H01L21/2885 , H01L21/7685 , H01L21/76885 , H01L21/76898 , H01L23/525 , H01L23/53214 , H01L23/53228 , H01L23/53242 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0345 , H01L2224/03462 , H01L2224/0347 , H01L2224/03616 , H01L2224/0391 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05005 , H01L2224/05018 , H01L2224/05023 , H01L2224/05025 , H01L2224/05026 , H01L2224/05099 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/05164 , H01L2224/05166 , H01L2224/0518 , H01L2224/05181 , H01L2224/05184 , H01L2224/05541 , H01L2224/05567 , H01L2224/05568 , H01L2224/05571 , H01L2224/0558 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/0568 , H01L2224/05681 , H01L2224/05684 , H01L2224/1131 , H01L2224/1134 , H01L2224/11849 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2924/00011 , H01L2924/00014 , H01L2924/01322 , H01L2924/12042 , H01L2924/00012 , H01L2924/207 , H01L2224/05552 , H01L2924/00 , H01L2924/014 , H01L2224/81805
摘要： An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.
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