公开(公告)号：US12130551B2

公开(公告)日：2024-10-29

申请号：US18335232

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Hao Lee ,  You-Cheng Jhang ,  Han-Zong Pan ,  Jui-Chun Weng ,  Chiu-Hua Chung ,  Sheng-Yuan Lin ,  Hsin-Yu Chen

IPC: G03F1/64 ,  G03F1/62 ,  G03F7/00

CPC classification number: G03F1/64 ,  G03F1/62 ,  G03F7/70983

Abstract: A photomask assembly may be formed such that stress relief trenches are formed in a pellicle frame of the photomask assembly. The stress relief trenches may reduce or prevent damage to a pellicle that may otherwise result from deformation of the pellicle. The stress relief trenches may be formed in areas of the pellicle frame to allow the pellicle frame to deform with the pellicle, thereby reducing the amount damage to the pellicle caused by the pellicle frame.

公开(公告)号：US12068597B2

公开(公告)日：2024-08-20

申请号：US17810602

申请日：2022-07-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Pin-Hsin Chang ,  Hsin-Yu Chen ,  Tzu-Heng Chang

IPC: H02H9/00 ,  H03K5/13 ,  H03K5/00

CPC classification number: H02H9/005 ,  H03K5/13 ,  H03K2005/00195

Abstract: The present disclosure provides a power clamp device. The power clamp device includes a delay element, a first transistor, a second transistor, and a gate control circuit. The delay element has an input terminal and an output terminal. The first transistor has a gate electrically connected to the output terminal of the delay element. The second transistor has a source electrically connected to a drain of the first transistor. The gate control circuit has a first terminal electrically connected to the input terminal of the delay element, a second terminal electrically connected to the output terminal of the delay element, and a third terminal electrically connected to a gate of the second transistor.

公开(公告)号：US11726401B2

公开(公告)日：2023-08-15

申请号：US17815328

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Hao Lee ,  You-Cheng Jhang ,  Han-Zong Pan ,  Jui-Chun Weng ,  Chiu-Hua Chung ,  Sheng-Yuan Lin ,  Hsin-Yu Chen

IPC: G03F1/64 ,  G03F1/62 ,  G03F7/20 ,  G03F7/00

CPC classification number: G03F1/64 ,  G03F1/62 ,  G03F7/70983

Abstract: A photomask assembly may be formed such that stress relief trenches are formed in a pellicle frame of the photomask assembly. The stress relief trenches may reduce or prevent damage to a pellicle that may otherwise result from deformation of the pellicle. The stress relief trenches may be formed in areas of the pellicle frame to allow the pellicle frame to deform with the pellicle, thereby reducing the amount damage to the pellicle caused by the pellicle frame.

公开(公告)号：US20220285339A1

公开(公告)日：2022-09-08

申请号：US17351111

申请日：2021-06-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Tzu-Heng Chang ,  Hsin-Yu Chen ,  Pin-Hsin Chang

IPC: H01L27/02 ,  H02H9/04

Abstract: The present disclosure provides electrostatic discharge circuits and structures and methods for operating the electrostatic discharge circuits and structures. A circuit includes a first transistor and a second transistor. The first transistor includes a drain, a source, a gate, and a bulk. The drain of the first transistor is connected to a first terminal. The source of the first transistor is connected to receive a first voltage. The gate and the bulk of the first transistor is connected to receive a second voltage. The second transistor includes a drain, a source, a gate, and a bulk. The source, the gate, and the bulk of the second transistor is connected to receive the second voltage. The drain of the second transistor is connected to the first terminal. In response to the terminal reaching a trigger voltage, the first transistor is configured to be turned on.

公开(公告)号：US10510641B2

公开(公告)日：2019-12-17

申请号：US15269753

申请日：2016-09-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yung-Chi Lin ,  Hsin-Yu Chen ,  Ming-Tsu Chung ,  HsiaoYun Lo ,  Hong-Ye Shih ,  Chia-Yin Chen ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/48 ,  H01L21/768

Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.

公开(公告)号：US10290604B2

公开(公告)日：2019-05-14

申请号：US15837704

申请日：2017-12-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Lin-Chih Huang ,  Hung-An Teng ,  Hsin-Yu Chen ,  Tsang-Jiuh Wu ,  Cheng-Chieh Hsieh

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/78 ,  H01L23/538 ,  H01L23/498 ,  H01L21/683 ,  H01L25/065 ,  H01L25/00 ,  H01L23/14 ,  H01L21/56 ,  H01L23/31

Abstract: Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed on a first side of the RDLs. Dies are bonded to the first side of the RDLs using the first connectors. An encapsulant is formed on the first side of the RDLs around the dies. The carrier is de-bonded from the overlaying structure and second connectors are formed on a second side of the RDLs. The resulting structure in diced to form individual packages.

公开(公告)号：US20180145046A1

公开(公告)日：2018-05-24

申请号：US15863240

申请日：2018-01-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiao Yun Lo ,  Lin-Chih Huang ,  Tasi-Jung Wu ,  Hsin-Yu Chen ,  Yung-Chi Lin ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/00

Abstract: A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.

公开(公告)号：US20180012825A1

公开(公告)日：2018-01-11

申请号：US15713011

申请日：2017-09-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Yang ,  Ming-Tsu Chung ,  Hong-Ye Shih ,  Jiung Wu ,  Chen-Yu Tsai ,  Hsin-Yu Chen ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/544 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/544 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/03

Abstract: An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value.

公开(公告)号：US09093314B2

公开(公告)日：2015-07-28

申请号：US14579326

申请日：2014-12-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jing-Cheng Lin ,  Ya-Hsi Hwung ,  Hsin-Yu Chen ,  Po-Hao Tsai ,  Yan-Fu Lin ,  Cheng-Lin Huang ,  Fang Wen Tsai ,  Wen-Chih Chiou

IPC: H01L21/4763 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L23/488 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05099 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/1182 ,  H01L2224/11823 ,  H01L2224/1191 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13578 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/1369 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/16145 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A work piece includes a copper bump having a top surface and sidewalls. A protection layer is formed on the sidewalls, and not on the top surface, of the copper bump. The protection layer includes a compound of copper and a polymer, and is a dielectric layer.

Abstract translation: 工件包括具有顶表面和侧壁的铜凸块。 在铜凸块的侧壁而不是顶表面上形成保护层。 保护层包括铜和聚合物的化合物，并且是介电层。

公开(公告)号：US20150130058A1

公开(公告)日：2015-05-14

申请号：US14604294

申请日：2015-01-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Yu Chen ,  Lin-Chih Huang ,  Tsang-Jiuh Wu ,  Tasi-Jung Wu ,  Wen-Chih Chiou

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L24/14 ,  H01L21/6835 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/96 ,  H01L25/0657 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/11424 ,  H01L2224/11464 ,  H01L2224/13025 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/96 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2224/81

Abstract: Methods of making and an integrated circuit device. An embodiment method includes patterning a first polymer layer disposed over a first copper seed layer, electroplating a through polymer via in the first polymer layer using the first copper seed layer, a via end surface offset from a first polymer layer surface, forming a second polymer layer over the first polymer layer, the second polymer layer patterned to expose the via end surface, and electroplating an interconnect in the second polymer layer to cap the via end surface using a second copper seed layer.

Abstract translation: 制造方法和集成电路器件。 一种实施方式包括图案化设置在第一铜籽晶层上的第一聚合物层，使用第一铜种子层在第一聚合物层中电镀穿过聚合物通孔，从第一聚合物层表面偏移的通孔端表面，形成第二聚合物 在第一聚合物层上方形成第二聚合物层，第二聚合物层图案化以暴露通孔端面，以及在第二聚合物层中电镀互连以通过第二铜种子层覆盖通孔端面。