公开(公告)号：US08254083B2

公开(公告)日：2012-08-28

申请号：US12851106

申请日：2010-08-05

申请人： Takashi Sakurai ,  Shinya Yoshihara ,  Ko Onodera ,  Hisayuki Abe ,  Masahiko Konno ,  Satoshi Kurimoto ,  Hiroshi Shindo ,  Akihiro Horita ,  Genichi Watanabe ,  Yoshikazu Ito

发明人： Takashi Sakurai ,  Shinya Yoshihara ,  Ko Onodera ,  Hisayuki Abe ,  Masahiko Konno ,  Satoshi Kurimoto ,  Hiroshi Shindo ,  Akihiro Horita ,  Genichi Watanabe ,  Yoshikazu Ito

IPC分类号： H01G4/06

CPC分类号： H01G4/2325 ,  B23K1/0016 ,  H01G4/30

摘要： There are provided a ceramic electronic component and a method for producing the ceramic electronic component, where a ground electrode layer can be directly coated with lead-free solder without lowering reliabilities. Terminal electrode 3 is provided with a ground electrode layer 21 of Cu having been formed by firing, a solder layer 22 formed of a lead-free solder based on five elements of Sn—Ag—Cu—Ni—Ge, and a diffusion layer 23 having been formed by the diffusion of Ni between the ground electrode layer 21 and the solder layer 22. Because the diffusion layer 23 of Ni is formed between the ground electrode layer 21 and the solder layer 22, the diffusion layer 23, which functions as a barrier layer, suppresses the solder leach of Cu from the ground electrode layer 21. The diffusion layer 23 of Ni can also suppress the growth of fragile intermetallic compounds of Sn—Cu. Therefore, a decrease in the bonding strength between the ground electrode layer 21 and the solder layer 22 can be prevented.

摘要翻译： 提供陶瓷电子部件和陶瓷电子部件的制造方法，其中接地电极层可以直接涂覆无铅焊料，而不降低可靠性。 端子电极3设置有通过烧制形成的Cu的接地电极层21，基于Sn-Ag-Cu-Ni-Ge的五个元素的无铅焊料形成的焊料层22和扩散层23 这是由于接地电极层21和焊料层22之间的Ni的扩散而形成的。由于在接地电极层21和焊料层22之间形成有Ni的扩散层23，所以作为 从接地电极层21抑制Cu的浸出.Ni的扩散层23也可以抑制Sn-Cu的易碎金属间化合物的生长。 因此，可以防止接地电极层21和焊料层22之间的接合强度的降低。

公开(公告)号：US20110051314A1

公开(公告)日：2011-03-03

申请号：US12851106

申请日：2010-08-05

申请人： Takashi SAKURAI ,  Shinya Yoshihara ,  Ko Onodera ,  Hisayuki Abe ,  Masahiko Konno ,  Satoshi Kurimoto ,  Hiroshi Shindo ,  Akihiro Horita ,  Genichi Watanabe ,  Yoshikazu Ito

发明人： Takashi SAKURAI ,  Shinya Yoshihara ,  Ko Onodera ,  Hisayuki Abe ,  Masahiko Konno ,  Satoshi Kurimoto ,  Hiroshi Shindo ,  Akihiro Horita ,  Genichi Watanabe ,  Yoshikazu Ito

IPC分类号： H01G4/06 ,  H01C7/10 ,  H01F27/28 ,  B23K1/20

CPC分类号： H01G4/2325 ,  B23K1/0016 ,  H01G4/30

摘要： There are provided a ceramic electronic component and a method for producing the ceramic electronic component, where a ground electrode layer can be directly coated with lead-free solder without lowering reliabilities. Terminal electrode 3 is provided with a ground electrode layer 21 of Cu having been formed by firing, a solder layer 22 formed of a lead-free solder based on five elements of Sn—Ag—Cu—Ni—Ge, and a diffusion layer 23 having been formed by the diffusion of Ni between the ground electrode layer 21 and the solder layer 22. Because the diffusion layer 23 of Ni is formed between the ground electrode layer 21 and the solder layer 22, the diffusion layer 23, which functions as a barrier layer, suppresses the solder leach of Cu from the ground electrode layer 21. The diffusion layer 23 of Ni can also suppress the growth of fragile intermetallic compounds of Sn—Cu. Therefore, a decrease in the bonding strength between the ground electrode layer 21 and the solder layer 22 can be prevented.

摘要翻译： 提供陶瓷电子部件和陶瓷电子部件的制造方法，其中接地电极层可以直接涂覆无铅焊料，而不降低可靠性。 端子电极3设置有通过烧制形成的Cu的接地电极层21，基于Sn-Ag-Cu-Ni-Ge的五个元素的无铅焊料形成的焊料层22和扩散层23 这是由于接地电极层21和焊料层22之间的Ni的扩散而形成的。由于在接地电极层21和焊料层22之间形成有Ni的扩散层23，所以作为 从接地电极层21抑制Cu的浸出.Ni的扩散层23也可以抑制Sn-Cu的易碎金属间化合物的生长。 因此，可以防止接地电极层21和焊料层22之间的接合强度的降低。

公开(公告)号：US08291585B2

公开(公告)日：2012-10-23

申请号：US12195772

申请日：2008-08-21

申请人： Ko Onodera ,  Satoshi Kurimoto ,  Hisayuki Abe ,  Taketo Sasaki ,  Yoji Tozawa ,  Osamu Hirose

发明人： Ko Onodera ,  Satoshi Kurimoto ,  Hisayuki Abe ,  Taketo Sasaki ,  Yoji Tozawa ,  Osamu Hirose

IPC分类号： H01R9/00 ,  H05K3/00

CPC分类号： H01G4/2325 ,  H01G4/30 ,  Y10T29/417 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49149 ,  Y10T29/49155

摘要： A chip element in the form of a substantially rectangular parallelepiped having end surfaces and side surfaces is formed (step of forming chip element). An electrically conductive green sheet is formed (step of forming electrically conductive green sheet). An electrically conductive paste is applied to the end surfaces of the chip element (step of application electrically conductive paste). A chip element is formed in which the electrically conductive green sheet is attached to the end surface via the electrically conductive paste applied to the end surface of the chip element (step of attaching electrically conductive sheet). In the step of attaching, the end surface of the electrically conductive green sheet on the side of the side surfaces is positioned on the outside of the side surfaces, and the electrically conductive paste applied to the end surface is pressed out into a space between the electrically conductive green sheet and ridge portions.

摘要翻译： 形成具有端面和侧面的大致长方体形状的芯片元件（形成芯片元件的步骤）。 形成导电性生片（形成导电性生片的工序）。 在芯片元件的端面施加导电性糊剂（涂敷导电糊剂的步骤）。 形成芯片元件，其中导电生片通过施加到芯片元件的端面上的导电膏（附着导电片的步骤）附着到端表面。 在安装的步骤中，导电性生片在侧面侧的端面位于侧面的外侧，并且施加到端面的导电糊被压出到 导电生片和脊部。

公开(公告)号：US20090053853A1

公开(公告)日：2009-02-26

申请号：US12195772

申请日：2008-08-21

申请人： Ko Onodera ,  Satoshi Kurimoto ,  Hisayuki Abe ,  Taketo Sasaki ,  Yoji Tozawa ,  Osamu Hirose

发明人： Ko Onodera ,  Satoshi Kurimoto ,  Hisayuki Abe ,  Taketo Sasaki ,  Yoji Tozawa ,  Osamu Hirose

IPC分类号： H01R43/00 ,  H01L21/00

CPC分类号： H01G4/2325 ,  H01G4/30 ,  Y10T29/417 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49149 ,  Y10T29/49155

摘要： A chip element in the form of a substantially rectangular parallelepiped having end surfaces and side surfaces is formed (step of forming chip element). An electrically conductive green sheet is formed (step of forming electrically conductive green sheet). An electrically conductive paste is applied to the end surfaces of the chip element (step of application electrically conductive paste). A chip element is formed in which the electrically conductive green sheet is attached to the end surface via the electrically conductive paste applied to the end surface of the chip element (step of attaching electrically conductive sheet). In the step of attaching, the end surface of the electrically conductive green sheet on the side of the side surfaces is positioned on the outside of the side surfaces, and the electrically conductive paste applied to the end surface is pressed out into a space between the electrically conductive green sheet and ridge portions.

摘要翻译： 形成具有端面和侧面的大致长方体形状的芯片元件（形成芯片元件的步骤）。 形成导电性生片（形成导电性生片的工序）。 在芯片元件的端面施加导电性糊剂（涂敷导电糊剂的步骤）。 形成芯片元件，其中导电生片通过施加到芯片元件的端面上的导电膏（附着导电片的步骤）附着到端表面。 在安装的步骤中，导电性生片在侧面侧的端面位于侧面的外侧，并且施加到端面的导电糊被压出到 导电生片和脊部。

公开(公告)号：US20100202098A1

公开(公告)日：2010-08-12

申请号：US12686651

申请日：2010-01-13

申请人： Miyuki YANAGIDA ,  Taketo Sasaki ,  Satoshi Kurimoto ,  Masahiko Konno ,  Yuki Morita ,  Hisayuki Abe

发明人： Miyuki YANAGIDA ,  Taketo Sasaki ,  Satoshi Kurimoto ,  Masahiko Konno ,  Yuki Morita ,  Hisayuki Abe

IPC分类号： H01G4/008 ,  H01G4/12

CPC分类号： H01G4/30 ,  H01G4/232 ,  H01G4/2325

摘要： A ceramic electronic part 100 having a chip element 1 having internal electrodes embedded therein, and terminal electrodes 3 that cover the end faces 11 of the chip element 1 having an exposed internal electrode and parts of the side faces 13,15 orthogonal to the end faces 11, and that are electrically connected to the internal electrodes, wherein the terminal electrodes 3 include a first electrode layer and a second electrode layer with a lower glass component content than the first electrode layer, in that order from the chip element 1 side, the second electrode layer being formed covering part of the first electrode layer on the side faces 13,15.

摘要翻译： 具有嵌入有内部电极的芯片元件1的陶瓷电子部件100和覆盖具有暴露的内部电极的芯片元件1的端面11和与端面正交的部分侧面13,15的端子电极3 11，并且与内部电极电连接，其中端子电极3包括第一电极层和具有比第一电极层低的玻璃成分含量的第二电极层，从芯片元件1侧起依次为 第二电极层被形成为覆盖在侧面13,15上的第一电极层的一部分。

公开(公告)号：US20110317328A1

公开(公告)日：2011-12-29

申请号：US13166993

申请日：2011-06-23

申请人： Susumu TANIGUCHI ,  Satoshi Kurimoto ,  Shintaro Tokumitsu ,  Ryugen Yanagibashi ,  Miyuki Yanagida ,  Hisayuki Abe

发明人： Susumu TANIGUCHI ,  Satoshi Kurimoto ,  Shintaro Tokumitsu ,  Ryugen Yanagibashi ,  Miyuki Yanagida ,  Hisayuki Abe

IPC分类号： H01G4/12 ,  H01C7/10

CPC分类号： H01G4/12 ,  H01G4/005 ,  H01G4/228 ,  H01G4/232 ,  H01G4/30

摘要： An array-type ceramic electronic component C1 includes a ceramic body 1 in which internal electrodes are buried and a plurality of terminal electrodes 11 to 16 formed on the ceramic body 1. The terminal electrodes 11 to 16 have electrode layers formed by baking a conductive green sheet.

摘要翻译： 阵列型陶瓷电子部件C1包括埋设有内部电极的陶瓷体1和形成在陶瓷体1上的多个端子电极11〜16。端子电极11〜16具有通过将导电性绿色 片。

公开(公告)号：US08183463B2

公开(公告)日：2012-05-22

申请号：US12869095

申请日：2010-08-26

申请人： Atsushi Sato ,  Hisayuki Abe ,  Takashi Ota ,  Miyuki Yanagida ,  Masumi Kameda

发明人： Atsushi Sato ,  Hisayuki Abe ,  Takashi Ota ,  Miyuki Yanagida ,  Masumi Kameda

IPC分类号： H05K1/09

CPC分类号： H05K3/244 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/3442 ,  H05K2201/10636 ,  H05K2203/1476 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T428/12458 ,  Y10T428/12889

摘要： The present invention provides a plating film 50 including a nickel plating layer containing phosphorus and a gold plating layer formed on the nickel plating layer, wherein the nickel plating layer has a phosphorus content of 11 to 16 mass %, and wherein (3×σ×100)/X is 10 or less, where X and σ are the average value and standard deviation of the phosphorus content in a surface of the nickel plating layer on the gold plating layer side, respectively; and a module substrate 100 having the plating film 50.

摘要翻译： 本发明提供一种镀镍膜，它包括含镍的镀镍层和形成在镀镍层上的镀金层，其中镀镍层的磷含量为11〜16质量％，其中（3×＆ ×100）/ X为10以下，其中X和＆sgr; 分别是镀金层侧的镀镍层的表面的磷含量的平均值和标准偏差; 以及具有镀膜50的模块基板100。

公开(公告)号：US07547975B2

公开(公告)日：2009-06-16

申请号：US10900458

申请日：2004-07-28

申请人： Minoru Takaya ,  Hisayuki Abe ,  Kei Suzuki ,  Kosuke Takano ,  Kenichi Kawabata ,  Toshikazu Endo

发明人： Minoru Takaya ,  Hisayuki Abe ,  Kei Suzuki ,  Kosuke Takano ,  Kenichi Kawabata ,  Toshikazu Endo

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/82 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/04105 ,  H01L2224/05026 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/82039 ,  H01L2224/82138 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K1/185 ,  H01L2924/00 ,  H01L2224/05599

摘要： A module with embedded semiconductor IC of the present invention includes a first resin layer, a second resin layer, post electrodes passing through the first and second resin layers, and a semiconductor IC mounted as embedded between the first resin layer and the second resin layer. Stud bumps are formed on land electrodes of the semiconductor IC and positioned with respect to the post electrodes. Owing to this positioning of the stud bumps formed on the semiconductor IC with respect to the post electrodes, the planar position of the stud bumps is substantially fixed. As a result, it is possible to use a semiconductor IC having a very narrow electrode pitch of 100 μm or smaller, particularly of around 60 μm.

摘要翻译： 具有本发明的嵌入式半导体IC的模块包括：第一树脂层，第二树脂层，通过第一和第二树脂层的柱电极;以及安装在第一树脂层和第二树脂层之间的半导体IC。 在半导体IC的接地电极上形成有柱状突起，并相对于柱状电极配置。 由于在半导体IC上相对于柱状电极形成的柱状凸块的这种定位，螺柱凸块的平面位置基本上是固定的。 结果，可以使用非常窄的电极间距为100μm或更小，特别是约60μm的半导体IC。

公开(公告)号：US06915944B1

公开(公告)日：2005-07-12

申请号：US10089067

申请日：2000-10-05

申请人： Minoru Takaya ,  Hisayuki Abe

发明人： Minoru Takaya ,  Hisayuki Abe

IPC分类号： B23K35/02 ,  B23K35/36 ,  H05K3/30 ,  H05K3/34 ,  B23K1/20

CPC分类号： B23K35/3618 ,  B23K35/025 ,  B23K35/3613 ,  H05K3/305 ,  H05K3/3484 ,  H05K3/3489 ,  H05K2201/10977 ,  Y02P70/613

摘要： The present invention relates to a soldering flux, a soldering paste and a soldering method that achieve a sufficient degree of bonding strength even when components are mounted at a higher density, components are further miniaturized or components are mounted with a smaller pitch. A flux 3 contains an adhesive resin and a hardening agent. This flux or a soldering paste containing the flux is applied onto a component mounting board 1, and then, an electronic component 4 is mounted and soldered onto the component mounting board 1.

摘要翻译： 本发明涉及即使当部件以更高的密度安装时也能实现足够的接合强度的焊剂，焊膏和焊接方法，部件进一步小型化或部件以较小的间距安装。 焊剂3含有粘合树脂和硬化剂。 将这种焊剂或含有焊剂的焊膏施加到部件安装板1上，然后将电子部件4安装并焊接到部件安装板1上。

公开(公告)号：US09258905B2

公开(公告)日：2016-02-09

申请号：US13005838

申请日：2011-01-13

申请人： Tsutomu Yasui ,  Hisayuki Abe ,  Kenichi Kawabata ,  Tomoko Kitamura

发明人： Tsutomu Yasui ,  Hisayuki Abe ,  Kenichi Kawabata ,  Tomoko Kitamura

IPC分类号： H01R9/00 ,  H05K3/34 ,  B23K35/02 ,  B23K35/26 ,  B23K35/30

CPC分类号： H05K3/3463 ,  B23K35/0227 ,  B23K35/0244 ,  B23K35/025 ,  B23K35/262 ,  B23K35/3033 ,  C22C13/00 ,  C22C19/03 ,  H01L2224/16225 ,  H01L2924/19105 ,  H05K3/3484

摘要： A first solder is lead-free solder that contains no lead (Pb). The first solder includes a first metal that contains at least Sn; and a second metal that contains at least a Ni—Fe alloy. An electronic component built-in module may include an electronic component and a substrate on which the electronic component is installed, where a terminal of the electronic component and a terminal of the substrate are joined together by using the lead-free solder.

摘要翻译： 第一种焊料是不含铅（Pb）的无铅焊料。 第一焊料包括至少含有Sn的第一金属; 以及含有至少Ni-Fe合金的第二金属。 电子部件内置模块可以包括电子部件和其上安装有电子部件的基板，其中电子部件的端子和基板的端子通过使用无铅焊料接合在一起。