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38 条记录 (耗时 0.024 秒)

    Data output circuit
    5.
    发明授权
    Data output circuit 有权
    数据输出电路

    公开(公告)号：US08081095B2

    公开(公告)日：2011-12-20

    申请号：US12134525

    申请日：2008-06-06

    申请人： Yasuo Osawa ,  Hiroyuki Arai ,  Tetsuya Tokunaga ,  Yoshiyuki Yamagata

    发明人： Yasuo Osawa ,  Hiroyuki Arai ,  Tetsuya Tokunaga ,  Yoshiyuki Yamagata

    IPC分类号： H03M9/00

    CPC分类号： G09G3/3685

    摘要： A data output circuit includes: a data generating circuit configured to generate output data; and a serial output circuit configured to receive an address corresponding to the data generating circuit, hold a parallel data input during a time period over which the address is being received, and serially output the output data generated by the data generating circuit and the held parallel data in accordance with an output direction signal for directing output of the data.

    摘要翻译： 数据输出电路包括：数据产生电路，被配置为产生输出数据; 以及串行输出电路，被配置为接收对应于数据产生电路的地址，在接收地址的时间段内保持并行数据输入，并且串行输出由数据产生电路产生的输出数据和所保持的并行 根据用于引导数据输出的输出方向信号的数据。

    Serial data input system
    6.
    发明授权
    Serial data input system 有权
    串行数据输入系统

    公开(公告)号：US08018445B2

    公开(公告)日：2011-09-13

    申请号：US11542640

    申请日：2006-10-04

    申请人： Tetsuya Tokunaga ,  Hiroyuki Arai ,  Takeshi Kimura

    发明人： Tetsuya Tokunaga ,  Hiroyuki Arai ,  Takeshi Kimura

    IPC分类号： G09G5/00 ,  G06F3/038

    CPC分类号： G11C7/02 ,  G11C7/1036 ,  G11C7/1078 ,  G11C7/1087

    摘要： Increase in power consumption and increase in power supply noise of a serial data input system are suppressed, while clock skew is more easily prevented. The serial data input system of this invention includes a shift register that takes in and shifts serially transferred display data in synchronization with a clock SCL, a clock counter that counts the number of clock pulses of the clock SCL and outputs each of clock count signals BIT08, BIT16 and BIT24 when the counted number of the clock pulses of the clock SCL reaches each of count numbers 8, 16 and 24 respectively, and registers into each of which the data stored in the shift register is transferred and stored collectively and in parallel in response to each of the clock count signals BIT08, BIP16 and BIT24 respectively.

    摘要翻译： 抑制串行数据输入系统的功耗增加和电源噪声增加，同时更容易防止时钟偏移。 本发明的串行数据输入系统包括一个移位寄存器，其与时钟SCL同步地接收和移位串行传送的显示数据，时钟计数器对时钟SCL的时钟脉冲数进行计数，并输出每个时钟计数信号BIT08 ，BIT16和BIT24，当时钟SCL的时钟脉冲的计数数量分别达到计数数8,16和24的每一个时，并且寄存到每个存储在移位寄存器中的数据被共同并且并行存储 分别响应于每个时钟计数信号BIT08，BIP16和BIT24。

    Apparatus for making prills from melted substance
    7.
    发明授权
    Apparatus for making prills from melted substance 失效
    用于从熔化物质制造颗粒的装置

    公开(公告)号：US4220441A

    公开(公告)日：1980-09-02

    申请号：US960692

    申请日：1978-11-14

    申请人： Shoji Tomita ,  Tetsuya Tokunaga

    发明人： Shoji Tomita ,  Tetsuya Tokunaga

    IPC分类号： C08J3/12 ,  B01J2/02 ,  B05B1/00 ,  B29B9/00 ,  B22D11/01

    CPC分类号： B01J2/02

    摘要： An improved prilling tower is provided for the prilling of molten substances wherein a receiver equipped with an exhaust conduit is positioned below the nozzle during pre-heating of the nozzle prior to normal operation, after the end of a normal operating cycle or when the nozzle is replaced during operation of the prilling tower. Means are provided for moving either the receiver or the nozzle in a horizontal direction so that the nozzle is out of proximity with the receiver during normal operation of the prilling tower. More than one nozzle or more than one receiver can be employed in a prilling tower to provide for continuous operation of the prilling tower during replacement or cleaning of the nozzles.

    摘要翻译： 提供了一种改进的造粒塔，用于造粒熔融物质，其中在正常操作之前，在正常操作循环结束之后，或者当喷嘴是在正常操作循环结束时，配备有排气导管的接收器在喷嘴预热之前位于喷嘴下方 在造血塔的运作期间更换。 提供了用于在水平方向上移动接收器或喷嘴的装置，使得在造粒塔的正常操作期间喷嘴与接收器不接近。 可以在造粒塔中使用多于一个的喷嘴或多于一个的接收器，以在更换或清洁喷嘴期间提供造粒塔的连续操作。

    Interface circuit and a clock output method therefor
    8.
    发明授权
    Interface circuit and a clock output method therefor 有权
    接口电路及其时钟输出方法

    公开(公告)号：US07724060B2

    公开(公告)日：2010-05-25

    申请号：US11736913

    申请日：2007-04-18

    申请人： Tetsuya Tokunaga ,  Hiroyuki Arai ,  Shuji Motegi ,  Takeshi Hibino ,  Takeshi Kimura

    发明人： Tetsuya Tokunaga ,  Hiroyuki Arai ,  Shuji Motegi ,  Takeshi Hibino ,  Takeshi Kimura

    IPC分类号： G05F1/04 ,  H03K3/00

    CPC分类号： G06F1/04

    摘要： An interface circuit outputting a clock signal and data to a data register configured to serially read in the data synchronously with the clock signal, in response to a change of a control signal for outputting the clock signal and the data from one logic level to the other logic level, the interface circuit comprising a clock output circuit configured to: detect a logic level of the clock signal when the control signal changes from the one logic level to the other logic level; output the clock signal on an as-is basis to the data register, when detecting one logic level of the clock signal; and output the clock signal after having changed from the other logic level to the one logic level, to the data register, when detecting the other logic level of the clock signal.

    摘要翻译： 一个接口电路，响应于用于输出时钟信号的控制信号和从一个逻辑电平到另一个逻辑电平的数据的变化，输出时钟信号和数据到数据寄存器，配置为与时钟信号同步地串行读取数据 逻辑电平，所述接口电路包括时钟输出电路，所述时钟输出电路被配置为：当所述控制信号从所述一个逻辑电平改变到另一逻辑电平时，检测所述时钟信号的逻辑电平; 当检测到时钟信号的一个逻辑电平时，将时钟信号原样输出到数据寄存器; 并且当检测到时钟信号的另一个逻辑电平时，在从另一个逻辑电平变为一个逻辑电平之后输出时钟信号到数据寄存器。

    Data Output Circuit
    9.
    发明申请
    Data Output Circuit 有权
    数据输出电路

    公开(公告)号：US20080303761A1

    公开(公告)日：2008-12-11

    申请号：US12134525

    申请日：2008-06-06

    申请人： Yasuo Osawa ,  Hiroyuki Arai ,  Tetsuya Tokunaga ,  Yoshiyuki Yamagata

    发明人： Yasuo Osawa ,  Hiroyuki Arai ,  Tetsuya Tokunaga ,  Yoshiyuki Yamagata

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3685

    摘要： A data output circuit includes: a data generating circuit configured to generate output data; and a serial output circuit configured to receive an address corresponding to the data generating circuit, hold a parallel data input during a time period over which the address is being received, and serially output the output data generated by the data generating circuit and the held parallel data in accordance with an output direction signal for directing output of the data.

    摘要翻译： 数据输出电路包括：数据产生电路，被配置为产生输出数据; 以及串行输出电路，被配置为接收对应于数据产生电路的地址，在接收地址的时间段内保持并行数据输入，并且串行输出由数据产生电路产生的输出数据和所保持的并行 根据用于引导数据输出的输出方向信号的数据。

    Frequency adjustment circuit
    10.
    发明申请
    Frequency adjustment circuit 有权
    频率调节电路

    公开(公告)号：US20060033583A1

    公开(公告)日：2006-02-16

    申请号：US11196512

    申请日：2005-08-04

    申请人： Tetsuya Tokunaga ,  Hiroyuki Arai ,  Takeshi Kimura ,  Ryouichi Ando ,  Mamoru Yamaguchi

    发明人： Tetsuya Tokunaga ,  Hiroyuki Arai ,  Takeshi Kimura ,  Ryouichi Ando ,  Mamoru Yamaguchi

    IPC分类号： H03L7/00

    CPC分类号： H03K3/0231 ,  H03K2005/00084

    摘要： A frequency adjustment circuit that maintains a target frequency even when frequency adjustment data of zapping circuit is changed by an external noise is offered. The frequency adjustment circuit includes a reset signal generation circuit, a frequency adjustment data latch circuit that latches and retains the frequency adjustment data ZP1 and ZP2 generated by a first zapping circuit and a second zapping circuit based on a latch clock ZCLK and a latch clock generation circuit that generates the latch clock ZCLK. The reset signal generation circuit generates a periodic reset signal ZRES that is synchronized with a rise of an enable signal EN generated from an interface circuit. The latch clock generation circuit generates the latch clock ZCLK that is synchronized with a fall of the enable signal EN.

    摘要翻译： 提供即使在由于外部噪声而使切换电路的频率调整数据变化的情况下也能够维持目标频率的频率调整电路。 频率调整电路包括复位信号生成电路，频率调整数据锁存电路，其锁存并保持由第一切换电路产生的频率调整数据ZP 1和ZP 2，以及基于锁存时钟ZCLK和锁存器的第二切换电路 时钟生成电路，生成锁存时钟ZCLK。 复位信号产生电路产生与从接口电路产生的使能信号EN的上升同步的周期性复位信号ZRES。 锁存时钟产生电路产生与使能信号EN的下降同步的锁存时钟ZCLK。