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    Mitigation of asymmetrical profile in self aligned patterning etch
    1.
    发明授权
    Mitigation of asymmetrical profile in self aligned patterning etch 有权
    减少自对准图案蚀刻中的不对称轮廓

    公开(公告)号：US09257280B2

    公开(公告)日：2016-02-09

    申请号：US14294278

    申请日：2014-06-03

    Applicant: TOKYO ELECTRON LIMITED

    Inventor： Akiteru Ko ,  Angelique D. Raley ,  Kiyohito Ito

    IPC: H01L21/308 ,  H01L21/33 ,  H01L21/033 ,  H01L21/311

    CPC classification number: H01L21/0337 ,  H01L21/3086 ,  H01L21/31144

    Abstract: A method which is particularly advantageous for improving a Self-Aligned Pattern (SAP) etching process. In such a process, facets formed on a spacer layer can cause undesirable lateral etching in an underlying layer beneath the spacer layer when the underlying layer is to be etched. This detracts from the desired vertical form of the etch. The etching of the underlying layer is performed in at least two steps, with a passivation layer or protective layer formed between the etch steps, so that sidewalls of the underlying layer that was partially etched during the initial etching are protected. After the protective layer is formed, the etching of the remaining portions of the underlying layer can resume.

    Abstract translation: 一种特别有利于改进自对准图案（SAP）蚀刻工艺的方法。 在这种过程中，当衬底层被蚀刻时，形成在间隔层上的刻面可能在间隔层下面的下层中产生不期望的横向蚀刻。 这会损害所需垂直形式的蚀刻。 底层的蚀刻在至少两个步骤中进行，其中在蚀刻步骤之间形成钝化层或保护层，使得在初始蚀刻期间被部分蚀刻的下层的侧壁被保护。 在形成保护层之后，可以恢复下层的其余部分的蚀刻。

    PARTIAL ETCH MEMORIZATION VIA FLASH ADDITION
    2.
    发明申请
    PARTIAL ETCH MEMORIZATION VIA FLASH ADDITION 有权
    部分记忆通过闪存添加

    公开(公告)号：US20160293435A1

    公开(公告)日：2016-10-06

    申请号：US15085186

    申请日：2016-03-30

    Applicant: Tokyo Electron Limited

    Inventor： Elliott Franke ,  Vinayak Rastogi ,  Akiteru Ko ,  Kiyohito Ito

    IPC: H01L21/3065 ,  H01L21/67 ,  H01J37/32 ,  H01L21/308

    CPC classification number: H01L21/30655 ,  H01J37/32009 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/67069

    Abstract: Provided is a method of creating structure profiles on a substrate using faceting and passivation layers. A first plasma etch process performed generating a faceted sidewall and a desired inflection point; a second plasma etch process is performed using an oxygen, nitrogen, or combined oxygen and nitrogen plasma, generating a passivation layer; and a third plasma etch process using operating variables of an etch chemistry on the faceted sidewall and the passivation layer to induce differential etch rates to achieve a breakthrough on near-horizontal surfaces of the structure, wherein the third plasma etch used is configured to produce a target sidewall profile on the substrate down to the underlying stop layer. Selected two or more plasma etch variables are controlled in the performance of the first plasma etch process, the second plasma etch process, and/or the third plasma etch process in order to achieve target sidewall profile objectives.

    Abstract translation: 提供了使用刻面和钝化层在基底上产生结构轮廓的方法。 执行产生刻面侧壁和期望拐点的第一等离子体蚀刻工艺; 使用氧，氮或组合的氧和氮等离子体进行第二等离子体蚀刻工艺，产生钝化层; 以及使用刻蚀侧壁和钝化层上的蚀刻化学品的操作变量的第三等离子体蚀刻工艺，以诱导差分蚀刻速率以在结构的近水平表面上实现突破，其中所用的第三等离子体蚀刻被配置为产生 基板上的目标侧壁轮廓直到底层停止层。 在第一等离子体蚀刻工艺，第二等离子体蚀刻工艺和/或第三等离子体蚀刻工艺的性能中控制所选择的两个或更多个等离子蚀刻变量，以实现目标侧壁轮廓目标。

    Etching method
    4.
    发明授权
    Etching method 有权

    公开(公告)号：US10950458B2

    公开(公告)日：2021-03-16

    申请号：US16238612

    申请日：2019-01-03

    Applicant: Tokyo Electron Limited

    Inventor： Yasutaka Hama ,  Shinya Morikita ,  Kiyohito Ito

    IPC: H01L21/311 ,  H01L21/768 ,  H01L21/67 ,  H01J37/32

    Abstract: An etching method is provided. The etching method is performed on a substrate having a first film to a third film. The third film is provided on an underlying region, the second film is provided on the third film, the first film is provided on the second film. The second film contains silicon and nitrogen. The first film to the third film are etched in sequence. Plasma of a processing gas containing fluorine and hydrogen is used in the etching of the first film to the third film. A temperature of the substrate is set to be equal to or less than 20° C. at least in the etching of the second film.

    Partial etch memorization via flash addition
    5.
    发明授权
    Partial etch memorization via flash addition 有权
    通过闪光加法部分蚀刻记忆

    公开(公告)号：US09576812B2

    公开(公告)日：2017-02-21

    申请号：US15085186

    申请日：2016-03-30

    Applicant: Tokyo Electron Limited

    Inventor： Elliott Franke ,  Vinayak Rastogi ,  Akiteru Ko ,  Kiyohito Ito

    IPC: H01L21/311 ,  H01L21/3065 ,  H01J37/32 ,  H01L21/308 ,  H01L21/67

    CPC classification number: H01L21/30655 ,  H01J37/32009 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/67069

    Abstract: Provided is a method of creating structure profiles on a substrate using faceting and passivation layers. A first plasma etch process performed generating a faceted sidewall and a desired inflection point; a second plasma etch process is performed using an oxygen, nitrogen, or combined oxygen and nitrogen plasma, generating a passivation layer; and a third plasma etch process using operating variables of an etch chemistry on the faceted sidewall and the passivation layer to induce differential etch rates to achieve a breakthrough on near-horizontal surfaces of the structure, wherein the third plasma etch used is configured to produce a target sidewall profile on the substrate down to the underlying stop layer. Selected two or more plasma etch variables are controlled in the performance of the first plasma etch process, the second plasma etch process, and/or the third plasma etch process in order to achieve target sidewall profile objectives.

    Abstract translation: 提供了使用刻面和钝化层在基底上产生结构轮廓的方法。 执行产生刻面侧壁和期望拐点的第一等离子体蚀刻工艺; 使用氧，氮或组合的氧和氮等离子体进行第二等离子体蚀刻工艺，产生钝化层; 以及使用刻蚀侧壁和钝化层上的蚀刻化学品的操作变量的第三等离子体蚀刻工艺，以诱导差分蚀刻速率以在结构的近水平表面上实现突破，其中所用的第三等离子体蚀刻被配置为产生 基板上的目标侧壁轮廓直到底层停止层。 在第一等离子体蚀刻工艺，第二等离子体蚀刻工艺和/或第三等离子体蚀刻工艺的性能中控制所选择的两个或更多个等离子蚀刻变量，以实现目标侧壁轮廓目标。

    Material processing to achieve sub-10nm patterning
    10.
    发明授权
    Material processing to achieve sub-10nm patterning 有权
    材料加工实现亚10nm图案化

    公开(公告)号：US09443731B1

    公开(公告)日：2016-09-13

    申请号：US14627501

    申请日：2015-02-20

    Applicant: Tokyo Electron Limited

    Inventor： David L. O'Meara ,  Angelique D. Raley ,  Akiteru Ko ,  Kiyohito Ito

    IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/311

    CPC classification number: H01L21/823431 ,  H01J37/32082 ,  H01J37/32192 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32105 ,  H01L21/32139

    Abstract: Provided is a method for increasing pattern density on a substrate comprising a structure with a patterned layer with a first composition and a sidewall and a cap layer of a second composition formed atop said structure. The sidewall is exposed to a chemical environment and creates a chemically modified sidewall layer of a third composition. The cap layer and an interior, non-modified portion of said structure is removed using an etching process to leave behind said chemically modified sidewall layer. A pattern transfer etch of said sidewall chemically modified layer onto the underlying layer of said substrate is performed. One or more integration operating variables are controlled to achieve target critical dimensions comprising width, height, sidewall angle, line width roughness, and/or line edge roughness of said structure.

    Abstract translation: 提供了一种用于增加衬底上的图案密度的方法，其包括具有第一组成的图案层的结构，以及形成在所述结构顶部的侧壁和第二组合物的盖层。 侧壁暴露于化学环境并产生第三组合物的化学改性的侧壁层。 使用蚀刻工艺除去所述结构的盖层和内部未改性部分，以留下所述化学改性的侧壁层。 执行所述侧壁化学改性层到所述衬底的下层上的图案转移蚀刻。 控制一个或多个集成操作变量以实现包括所述结构的宽度，高度，侧壁角度，线宽粗糙度和/或线边缘粗糙度的目标临界尺寸。

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