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    Method for forming a microwave field effect transistor with high operating voltage
    2.
    发明授权
    Method for forming a microwave field effect transistor with high operating voltage 有权
    用于形成具有高工作电压的微波场效应晶体管的方法

    公开(公告)号：US06867078B1

    公开(公告)日：2005-03-15

    申请号：US10716955

    申请日：2003-11-19

    申请人： Bruce M. Green ,  Olin L. Hartin ,  Lawrence S. Klingbeil ,  Ellen Y. Lan ,  Hsin-Hua P. Li ,  Charles E. Weitzel

    发明人： Bruce M. Green ,  Olin L. Hartin ,  Lawrence S. Klingbeil ,  Ellen Y. Lan ,  Hsin-Hua P. Li ,  Charles E. Weitzel

    IPC分类号： H01L21/335 ,  H01L29/423 ,  H01L29/778 ,  H01L21/338 ,  H01L21/3205

    CPC分类号： H01L29/66462 ,  H01L29/42316 ,  H01L29/7785

    摘要： A microwave field effect transistor (10) has a high conductivity gate (44) overlying a double heterojunction structure (14, 18, 22) that has an undoped channel layer (18). The heterojunction structure overlies a substrate (12). A recess layer that is a not intentionally doped (NID) layer (24) overlies the heterojunction structure and is formed with a predetermined thickness that minimizes impact ionization effects at an interface of a drain contact of source/drain ohmic contacts (30) and permits significantly higher voltage operation than previous step gate transistors. Another recess layer (26) is used to define a gate dimension. A Schottky gate opening (42) is formed within a step gate opening (40) to create a step gate structure. A channel layer (18) material of InxGa1−xAs is used to provide a region of electron confinement with improved transport characteristics that result in higher frequency of operation, higher power density and improved power-added efficiency.

    摘要翻译： 微波场效应晶体管（10）具有覆盖具有未掺杂沟道层（18）的双异质结结构（14,18,22）的高导电性栅极（44）。 异质结结构覆盖在基板（12）上。 作为非有意掺杂（NID）层（24）的凹陷层覆盖在异质结结构上并形成预定的厚度，使得在源极/漏极欧姆接触（30）的漏极接触的界面处的冲击电离效应最小化并允许 比上一级栅晶体管显着更高的电压操作。 另一个凹陷层（26）用于限定门尺寸。 肖特基门开口（42）形成在步进门开口（40）内以形成阶梯门结构。 使用In x Ga 1-x As的沟道层（18）材料来提供具有改善的传输特性的电子约束区域，这导致更高的操作频率，更高的功率密度和更好的功率附加效率。

    Method for patterning a substrate with photoresist
    4.
    发明授权
    Method for patterning a substrate with photoresist 失效
    用光刻胶图案化基板的方法

    公开(公告)号：US06391800B1

    公开(公告)日：2002-05-21

    申请号：US09439177

    申请日：1999-11-12

    申请人： Randy D. Redd ,  Lawrence S. Klingbeil

    发明人： Randy D. Redd ,  Lawrence S. Klingbeil

    IPC分类号： H01L2131

    CPC分类号： H01L21/0274 ,  G03F7/16 ,  G03F7/162 ,  H01L21/312

    摘要： A method for patterning a substrate having a surface with high aspect ratio topography with a photoresist is described. Specifically the surface of a semiconductor substrate is pre-wetted with a solvent solution to form a liquid solvent film. An additional amount of the solvent solution is added to form a solvent puddle on the liquid solvent film. Photoresist is dispensed onto the solvent puddle for a sufficient time and in a sufficient amount to allow diffusion of the photoresist and the solvent puddle into the openings defined in the topography of the substrate. The solvent solution in and on the surface of the openings defined in the substrate from the pre-wetting step is replaced with the photoresist by facilitating diffusion of the photoresist into the topography openings. A photoresist layer is then cast in a predetermined thickness on the surface of the substrate.

    摘要翻译： 描述了用光刻胶对具有高纵横比拓扑的表面进行图案化的方法。 具体地说，将半导体衬底的表面用溶剂溶液预润湿以形成液体溶剂膜。 加入额外量的溶剂溶液以在液体溶剂膜上形成溶剂池。 将光致抗蚀剂分配到溶剂池上足够的时间并且足够的量以使光致抗蚀剂和溶剂熔池扩散到限定在衬底的形貌中的开口中。 通过促进光致抗蚀剂扩散到形貌开口中，通过预润湿步骤限定在基底中的开口中和表面上的溶剂溶液被光致抗蚀剂代替。 然后将光致抗蚀剂层以预定厚度浇铸在基材的表面上。

    Method of manufacturing a semiconductor component that includes self-aligning a gate electrode to a field plate
    6.
    发明授权
    Method of manufacturing a semiconductor component that includes self-aligning a gate electrode to a field plate 失效
    制造半导体部件的方法，其包括将栅电极自对准到场板

    公开(公告)号：US06939781B2

    公开(公告)日：2005-09-06

    申请号：US10609106

    申请日：2003-06-27

    申请人： Randy D. Redd ,  Paul A. Fisher ,  Olin L. Hartin ,  Lawrence S. Klingbeil ,  Ellen Lan ,  Hsin-Hua P. Li ,  Charles E. Weitzel

    发明人： Randy D. Redd ,  Paul A. Fisher ,  Olin L. Hartin ,  Lawrence S. Klingbeil ,  Ellen Lan ,  Hsin-Hua P. Li ,  Charles E. Weitzel

    IPC分类号： H01L21/338 ,  H01L29/812 ,  H01L21/76

    CPC分类号： H01L29/66871 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/812

    摘要： In one embodiment of the invention, a semiconductor component includes a semiconductor substrate (110), a first dielectric layer (120) above the semiconductor substrate, a first ohmic contact region (410) and a second ohmic contact region (420) above the semiconductor substrate, a gate electrode (1120) above the semiconductor substrate and between the first ohmic contact region and the second ohmic contact region, a field plate (210) above the first dielectric layer and between the gate electrode and the second ohmic contact region, a second dielectric layer (310) above the field plate, the first dielectric layer, the first ohmic contact region, and the second ohmic contact region, and a third dielectric layer (910) between the gate electrode and the field plate and not located above the gate electrode or the field plate.

    摘要翻译： 在本发明的一个实施例中，半导体部件包括半导体衬底（110），半导体衬底上方的第一介电层（120），半导体上方的第一欧姆接触区（410）和第二欧姆接触区（420） 衬底，半导体衬底之上和第一欧姆接触区域和第二欧姆接触区域之间的栅极电极（1120），在第一介电层上方以及栅电极和第二欧姆接触区域之间的场板（210）， 位于场板上方的第二电介质层（310），第一电介质层，第一欧姆接触区域和第二欧姆接触区域，以及栅电极和场板之间的第三介电层（910） 栅电极或场板。