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    REGENERATED CUTTING BLADE AND SHEARING TYPE GRINDER
    2.
    发明申请
    REGENERATED CUTTING BLADE AND SHEARING TYPE GRINDER 审中-公开
    再生切割刀片和剪切型磨床

    公开(公告)号：US20150251188A1

    公开(公告)日：2015-09-10

    申请号：US14417344

    申请日：2012-08-28

    申请人： Naoya Wada ,  Naoki Ueno ,  Yasuhiko Honda ,  Isao Nagai

    发明人： Naoya Wada ,  Naoki Ueno ,  Yasuhiko Honda ,  Isao Nagai

    IPC分类号： B02C18/18 ,  B02C18/14

    CPC分类号： B02C18/184 ,  B02C18/142 ,  B02C18/145

    摘要： To present a regenerated cutting blade, capable of regenerating efficiently by saving the cost and labor for regenerating a cutting blade, and improved in the grinding efficiency of a shearing type grinder to be close to that of a new cutting blade, when mounted and used in a shearing type grinder, including a fixed part 125, and a blade tip 127 projecting outward from this fixed part 125, in which the blade tip 127 has a leading end edge 109 pointed toward the rotating direction, and side edges 110 on the lateral side outer periphery including the blade tip 127, the leading end edge 109 and the side edges 110 are regenerated and formed by build-up welding, and the lateral sides are provided with slip preventive build-up welding parts 111, 112, 113 of the workpiece extending from the side edges 110 toward the central side of its rotation or the central direction, being formed by three regenerating processes.

    摘要翻译： 为了提供能够通过节省用于再生切割刀片的成本和劳动力而有效地再生的再生切割刀片，并且将剪切式研磨机的研磨效率提高为接近于新的切割刀片的磨削效率，当安装和使用时 包括固定部分125的剪切式研磨机以及从该固定部125向外突出的叶片尖端127，其中叶片尖端127具有朝向旋转方向指向的前端边缘109，侧面侧的侧边缘110 包括叶片尖端127，前端缘109和侧边缘110的外周边通过堆积焊接再生和形成，并且侧边设置有工件的防滑成型焊接部111,112,113 从侧边缘110向其旋转中心方向或中心方向延伸，由三个再生过程形成。

    Nonvolatile semiconductor storage device
    3.
    发明授权
    Nonvolatile semiconductor storage device 有权
    非易失性半导体存储器件

    公开(公告)号：US08130545B2

    公开(公告)日：2012-03-06

    申请号：US12938435

    申请日：2010-11-03

    申请人： Yasuhiko Honda ,  Takahiro Suzuki ,  Masao Iwamoto ,  Kiyochika Kinjo

    发明人： Yasuhiko Honda ,  Takahiro Suzuki ,  Masao Iwamoto ,  Kiyochika Kinjo

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C29/00

    摘要： A nonvolatile semiconductor storage device capable of storing a plurality of bits of data in one memory cell by assigning multivalued data having a higher-order bit selected from one of a pair of data in a first unit and a lower-order bit selected from the other of the pair of data to each threshold voltage of the memory cell, wherein in a first write operation that processes data in the first unit, the logic of one of the higher-order bit and the lower-order bit is fixed, and two pieces of multivalued data that maximize the difference between the threshold voltages are assigned, thereby storing one bit of input data in the one memory cell in a pseudo binary state, and in a second write operation that processes data in a second unit larger than the first unit, a plurality of bits of input data is stored in the one memory cell in a multivalued state, and parity data for error correction in the second unit is stored in the memory cell.

    摘要翻译： 一种非易失性半导体存储装置，其能够通过分配具有从第一单位中选择的一对数据中的一个中选择的高阶位的多值数据和从另一个存储单元中选择的低位位来存储多个数据位在一个存储单元中 所述数据对与所述存储单元的每个阈值电压相关，其中在处理所述第一单元中的数据的第一写入操作中，所述高位和低位中的一个的逻辑被固定，并且两个 分配最大化阈值电压之间的差异的多值数据，从而将一位存储单元中的一位输入数据存储在伪二进制状态，并且在第二写入操作中处理大于第一单元的第二单元中的数据 输入数据的多个位以多值状态存储在一个存储单元中，第二单元中用于纠错的奇偶校验数据被存储在存储单元中。

    Nonvolatile semiconductor memory including charge accumulation layer and control gate
    5.
    发明授权
    Nonvolatile semiconductor memory including charge accumulation layer and control gate 失效
    非易失性半导体存储器，包括电荷累积层和控制栅极

    公开(公告)号：US07924620B2

    公开(公告)日：2011-04-12

    申请号：US12543161

    申请日：2009-08-18

    申请人： Yasuhiko Honda

    发明人： Yasuhiko Honda

    IPC分类号： G11C16/00

    CPC分类号： G11C8/08 ,  G11C16/0483 ,  G11C16/10

    摘要： A nonvolatile semiconductor memory includes a transistor, a first MOS, a second MOS, a first voltage circuit, and a second voltage circuit. The transistor includes a accumulation layer, a control gate, and a first impurity diffused layer. The first MOS includes a first electrode and a second layer. The second MOS includes a second electrode and a third layer, after the channels being formed, the first MOS and the second MOS being cut off. The first voltage circuit applies a first voltage to an active region to generate a forward bias. The second voltage circuit applies a second voltage, and a third voltage to the control gate of the transistor, after the first voltage circuit charges the first to third impurity diffused layer to the first voltage, the second voltage circuit applying the second voltage and the third voltage to the control gate of the transistor.

    摘要翻译： 非易失性半导体存储器包括晶体管，第一MOS，第二MOS，第一电压电路和第二电压电路。 晶体管包括累积层，控制栅极和第一杂质扩散层。 第一MOS包括第一电极和第二层。 第二MOS包括第二电极和第三层，在形成沟道之后，第一MOS和第二MOS被截止。 第一电压电路向有源区域施加第一电压以产生正向偏置。 在第一电压电路将第一至第三杂质扩散层充电至第一电压之后，第二电压电路将第二电压和第三电压施加到晶体管的控制栅极，施加第二电压的第二电压电路和施加第二电压的第二电压电路 电压到晶体管的控制栅极。

    Nonvolatile semiconductor storage device
    6.
    发明授权
    Nonvolatile semiconductor storage device 有权
    非易失性半导体存储器件

    公开(公告)号：US07843728B2

    公开(公告)日：2010-11-30

    申请号：US12272161

    申请日：2008-11-17

    申请人： Yasuhiko Honda ,  Takahiro Suzuki ,  Masao Iwamoto ,  Kiyochika Kinjo

    发明人： Yasuhiko Honda ,  Takahiro Suzuki ,  Masao Iwamoto ,  Kiyochika Kinjo

    IPC分类号： G11C16/04

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C29/00

    摘要： A nonvolatile semiconductor storage device capable of storing a plurality of bits of data in one memory cell by assigning multivalued data having a higher-order bit selected from one of a pair of data in a first unit and a lower-order bit selected from the other of the pair of data to each threshold voltage of the memory cell, wherein in a first write operation that processes data in the first unit, the logic of one of the higher-order bit and the lower-order bit is fixed, and two pieces of multivalued data that maximize the difference between the threshold voltages are assigned, thereby storing one bit of input data in the one memory cell in a pseudo binary state, and in a second write operation that processes data in a second unit larger than the first unit, a plurality of bits of input data is stored in the one memory cell in a multivalued state, and parity data for error correction in the second unit is stored in the memory cell.

    摘要翻译： 一种非易失性半导体存储装置，其能够通过分配具有从第一单位中选择的一对数据中的一个中选择的高阶位的多值数据和从另一个存储单元中选择的低位位来存储多个数据位在一个存储单元中 所述数据对与所述存储单元的每个阈值电压相关，其中在处理所述第一单元中的数据的第一写入操作中，所述高位和低位中的一个的逻辑被固定，并且两个 分配最大化阈值电压之间的差异的多值数据，从而将一位存储单元中的一位输入数据存储在伪二进制状态，并且在第二写入操作中处理大于第一单元的第二单元中的数据 输入数据的多个位以多值状态存储在一个存储单元中，第二单元中用于纠错的奇偶校验数据被存储在存储单元中。

    Semiconductor integrated circuit device and read start trigger signal generating method therefor
    10.
    发明授权
    Semiconductor integrated circuit device and read start trigger signal generating method therefor 有权
    半导体集成电路器件及其读取开始触发信号产生方法

    公开(公告)号：US06903983B2

    公开(公告)日：2005-06-07

    申请号：US10325753

    申请日：2002-12-23

    申请人： Tokumasa Hara ,  Hidetoshi Saito ,  Hitoshi Shiga ,  Yasuhiko Honda ,  Tadayuki Taura ,  Hideo Kato

    发明人： Tokumasa Hara ,  Hidetoshi Saito ,  Hitoshi Shiga ,  Yasuhiko Honda ,  Tadayuki Taura ,  Hideo Kato

    IPC分类号： G11C16/02 ,  G11C8/18 ,  G11C16/32 ,  G11C16/04

    CPC分类号： G11C8/18 ,  G11C16/32 ,  G11C2216/22

    摘要： A semiconductor integrated circuit device includes a first memory cell array corresponding to bank 0, a second memory cell array corresponding to bank 1, first address transition signal generating circuits which detect transitions of input addresses and generate first address transition signals, a second address transition signal generating circuit which pre-detects an end of automatic execution of bank 0 or bank 1 and generates a second address transition signal, and a read start trigger output circuit. The read start trigger output circuit outputs a read start trigger signal on the basis of the first address transition signals and the second address transition signal.

    摘要翻译： 半导体集成电路装置包括对应于存储体0的第一存储单元阵列，对应于存储体1的第二存储单元阵列，检测输入地址的转换并产生第一地址转换信号的第一地址转换信号产生电路，第二地址转换信号 生成电路，其预先检测存储体0或存储体1的自动执行结束并产生第二地址转换信号，以及读取开始触发输出电路。 读取开始触发输出电路基于第一地址转换信号和第二地址转换信号输出读取开始触发信号。