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    Semiconductor memory device requiring refresh operation
    3.
    发明授权
    Semiconductor memory device requiring refresh operation 失效
    需要刷新操作的半导体存储器件

    公开(公告)号：US06813210B2

    公开(公告)日：2004-11-02

    申请号：US10300591

    申请日：2002-11-21

    申请人： Takeo Okamoto ,  Tetsuichiro Ichiguchi ,  Hideki Yonetani ,  Tsutomu Nagasawa ,  Tadaaki Yamauchi ,  Makoto Suwa ,  Junko Matsumoto ,  Zengcheng Tian

    发明人： Takeo Okamoto ,  Tetsuichiro Ichiguchi ,  Hideki Yonetani ,  Tsutomu Nagasawa ,  Tadaaki Yamauchi ,  Makoto Suwa ,  Junko Matsumoto ,  Zengcheng Tian

    IPC分类号： G11C700

    CPC分类号： G11C7/04 ,  G11C11/406

    摘要： The semiconductor memory device includes a refresh timer for determining a refresh cycle of self-refresh operation. The refresh timer includes a voltage regulator, a ring oscillator and a counter. The voltage regulator generates a bias voltage having positive temperature characteristics. The ring oscillator varies an oscillation cycle of a pulse signal according to the bias voltage. The counter counts a prescribed number of pulse signals and generates a refresh signal for executing refresh operation. The semiconductor memory device thus varies the refresh cycle according to a temperature change, and executes refresh operation with an appropriate refresh cycle.

    摘要翻译： 半导体存储器件包括用于确定自刷新操作的刷新周期的刷新定时器。 刷新定时器包括电压调节器，环形振荡器和计数器。 电压调节器产生具有正温度特性的偏置电压。 环形振荡器根据偏置电压来改变脉冲信号的振荡周期。 计数器对规定数量的脉冲信号进行计数，并产生用于执行刷新操作的刷新信号。 因此，半导体存储器件根据温度变化而改变刷新周期，并且以适当的刷新周期执行刷新操作。

    Semiconductor memory device switchable to twin memory cell configuration
    7.
    发明授权
    Semiconductor memory device switchable to twin memory cell configuration 失效
    半导体存储器件可切换到双存储单元配置

    公开(公告)号：US06775177B2

    公开(公告)日：2004-08-10

    申请号：US10298648

    申请日：2002-11-19

    申请人： Takeo Okamoto ,  Tetsuichiro Ichiguchi ,  Hideki Yonetani ,  Tsutomu Nagasawa ,  Makoto Suwa ,  Zengcheng Tian ,  Tadaaki Yamauchi ,  Junko Matsumoto

    发明人： Takeo Okamoto ,  Tetsuichiro Ichiguchi ,  Hideki Yonetani ,  Tsutomu Nagasawa ,  Makoto Suwa ,  Zengcheng Tian ,  Tadaaki Yamauchi ,  Junko Matsumoto

    IPC分类号： G11C1124

    CPC分类号： G11C11/405 ,  G11C7/1045 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4087

    摘要： A row address decoder of a semiconductor memory device generates internal row address signals RAD and /RAD by switching most significant bit and least significant bit of row address signals RA and /RA that correspond to address signals A0 to A11, respectively. In a twin cell mode, the least significant bits RAD and /RAD of the internal row address signals corresponding to the most significant bits RA and /RA of the row address signal that are not used are selected simultaneously by row address decoder, and two adjacent word lines are activated simultaneously. Consequently, the configuration of memory cell in the semiconductor memory device can electrically be switched from the normal single memory cell type to the twin memory cell type.

    摘要翻译： 通过切换行地址信号RA <0:11>和/ RA的最高有效位和最低有效位，半导体存储器件的行地址解码器产生内部行地址信号RAD <0:11>和/ RAD <0:11> 分别对应于地址信号A0至A11的<0:11>。 在双胞模式中，对应于不是行地址信号的最高有效位RA 11和/ RA 11的内部行地址信号的最低有效位RAD <0>和/ RAD <0> 使用的同时由行地址解码器选择，并且两个相邻的字线同时被激活。 因此，半导体存储器件中的存储单元的配置可以从正常的单个存储器单元类型切换到双存储单元类型。

    Semiconductor storage unit
    8.
    发明授权
    Semiconductor storage unit 失效
    半导体存储单元

    公开(公告)号：US06775198B2

    公开(公告)日：2004-08-10

    申请号：US10253512

    申请日：2002-09-25

    申请人： Kozo Ishida ,  Hideki Yonetani ,  Takeshi Ohgami

    发明人： Kozo Ishida ,  Hideki Yonetani ,  Takeshi Ohgami

    IPC分类号： G11C700

    CPC分类号： G11C5/14

    摘要： Power to operates memory bank of DRAM stably is supplied with reduced power consumption. A semiconductor storage unit includes multiple arrays forming memory banks on a substrate, first and second power supplies. Multiple arrays are arranged like a matrix and surround the central region of the substrate. Each memory bank consists of two of the multiple arrays. Each first power supply supplies driving power to a peripheral circuit which drives each multiple array. Second power supplies are arranged at four corners of the central region, each supply provides access power to word lines which access the multiple arrays. The first power supplies are mounted to a central and the opposite side for predetermined arrays, serve as a main and an auxiliary power supply to provide main and auxiliary power (smaller than the main power), and provide distantly arranged two of the multiple arrays forming a memory bank with power.

    摘要翻译： 稳定地操作DRAM的存储体的功率被提供降低的功耗。 半导体存储单元包括在基板上形成存储体的多个阵列，第一和第二电源。 多个阵列被布置成像矩阵并且围绕衬底的中心区域。 每个存储体由多个阵列中的两个组成。 每个第一电源为驱动每个多阵列的外围电路提供驱动电力。 第二电源设置在中央区域的四个角处，每个电源为访问多个阵列的字线提供访问电力。 第一电源被安装到中央和相对侧用于预定的阵列，用作主电源和辅助电源，以提供主功率和辅助功率（小于主功率），并且提供形成的多个阵列中的远距离布置的两个 一个有权力的记忆库。