公开(公告)号：US06724679B2

公开(公告)日：2004-04-20

申请号：US10126622

申请日：2002-04-22

申请人： Tsutomu Nagasawa ,  Hideki Yonetani ,  Kozo Ishida ,  Shinichi Jinbo ,  Makoto Suwa ,  Tadaaki Yamauchi ,  Junko Matsumoto ,  Zengcheng Tian ,  Takeo Okamoto

发明人： Tsutomu Nagasawa ,  Hideki Yonetani ,  Kozo Ishida ,  Shinichi Jinbo ,  Makoto Suwa ,  Tadaaki Yamauchi ,  Junko Matsumoto ,  Zengcheng Tian ,  Takeo Okamoto

IPC分类号： G11C800

CPC分类号： G11C29/12005 ,  G11C8/12 ,  G11C29/26 ,  G11C2029/1206

摘要： A semiconductor memory device includes banks, predecoders, a latch circuit, a counter, a fuse and buffers. The bank includes a plurality of memory cells arranged in rows and columns, and others. The predecoders are disposed in a central portion of the semiconductor memory device. The predecoder produces a predecode signal for selecting each of the banks based on a bank address received from the buffer, and outputs the predecode signal to the banks. The predecoder produces the predecode signal for selecting each of the banks based on the bank address, and outputs the predecode signal to the banks. Consequently, interconnections in the central portion can be reduced in number.

摘要翻译： 半导体存储器件包括存储体，预解码器，锁存电路，计数器，熔丝和缓冲器。 存储体包括以行和列排列的多个存储单元。 预解码器设置在半导体存储器件的中心部分。 预解码器基于从缓冲器接收到的存储体地址产生用于选择每个存储体的预解码信号，并将预解码信号输出到存储体。 预解码器产生用于基于存储体地址选择每个存储体的预解码信号，并将预解码信号输出到存储体。 因此，可以减少中心部分的互连。

公开(公告)号：US06625050B2

公开(公告)日：2003-09-23

申请号：US10143931

申请日：2002-05-14

申请人： Makoto Suwa ,  Shinichi Jinbo ,  Zengcheng Tian ,  Takeo Okamoto ,  Kozo Ishida ,  Hideki Yonetani ,  Tsutomu Nagasawa ,  Tadaaki Yamauchi ,  Junko Matsumoto

发明人： Makoto Suwa ,  Shinichi Jinbo ,  Zengcheng Tian ,  Takeo Okamoto ,  Kozo Ishida ,  Hideki Yonetani ,  Tsutomu Nagasawa ,  Tadaaki Yamauchi ,  Junko Matsumoto

IPC分类号： G11C506

CPC分类号： B82Y10/00 ,  H01L23/50 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/13091 ,  H03K3/356008 ,  H01L2224/45099 ,  H01L2924/00

摘要： Pad lines are placed on the peripheral region of a chip along EAST band and WEST band (E/W band). In order to allow the chip with pads arranged on the peripheral region to be adaptable to a TSOP, VDD and VSS pads are arranged on the edge region on NORTH band and SOUTH band (N/S band) near the center of the N/S band. Moreover, in consideration of frame design for the TSOP, some pads on the ends of the pad lines among the pads included in the pad lines are arranged in reverse order relative to the order of pins. Further, VDDQ and VSSQ pads are arranged in the same order as that of pins for a package which requires no consideration of frame design. On the other hand, for use in a BGA package, VDD and VSS pads are arranged in pairs at respective ends of the pad lines. A semiconductor memory device with this pad arrangement is accordingly adaptable to various types of packages.

公开(公告)号：US06724223B2

公开(公告)日：2004-04-20

申请号：US10287643

申请日：2002-11-05

申请人： Tetsuichiro Ichiguchi ,  Tsutomu Nagasawa ,  Tadaaki Yamauchi ,  Zengcheng Tian ,  Makoto Suwa ,  Junko Matsumoto ,  Takeo Okamoto ,  Hideki Yonetani

发明人： Tetsuichiro Ichiguchi ,  Tsutomu Nagasawa ,  Tadaaki Yamauchi ,  Zengcheng Tian ,  Makoto Suwa ,  Junko Matsumoto ,  Takeo Okamoto ,  Hideki Yonetani

IPC分类号： H03K190175

CPC分类号： G11C7/225 ,  G11C5/14 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  H01L27/0255

摘要： A clock buffer of a DRAM includes: a first NAND gate which is driven by a first internal power supply voltage (2.5 V) and which determines the level of an input clock signal if the DRAM is used for a TTL-system interface (MLV=2.5 V); and a second NAND gate which is driven by a second internal power supply voltage (1.8 V) and which determines the level of the input clock signal if the DRAM is used for a 1.8 V-system interface (MLV=0 V). Accordingly, in each of the first and second NAND gates, sizes of four MOS transistors can be set at optimum values, respectively.

摘要翻译： DRAM的时钟缓冲器包括：第一NAND门，其由第一内部电源电压（2.5V）驱动，并且如果DRAM用于TTL系统接口，则确定输入时钟信号的电平（MLV = 2.5 V）; 以及第二NAND门，其由第二内部电源电压（1.8V）驱动，并且如果DRAM用于1.8V系统接口（MLV = 0V），则确定输入时钟信号的电平。 因此，在第一和第二NAND门的每一个中，四个MOS晶体管的尺寸可以分别被设定为最佳值。

公开(公告)号：US06813210B2

公开(公告)日：2004-11-02

申请号：US10300591

申请日：2002-11-21

申请人： Takeo Okamoto ,  Tetsuichiro Ichiguchi ,  Hideki Yonetani ,  Tsutomu Nagasawa ,  Tadaaki Yamauchi ,  Makoto Suwa ,  Junko Matsumoto ,  Zengcheng Tian

发明人： Takeo Okamoto ,  Tetsuichiro Ichiguchi ,  Hideki Yonetani ,  Tsutomu Nagasawa ,  Tadaaki Yamauchi ,  Makoto Suwa ,  Junko Matsumoto ,  Zengcheng Tian

IPC分类号： G11C700

CPC分类号： G11C7/04 ,  G11C11/406

摘要： The semiconductor memory device includes a refresh timer for determining a refresh cycle of self-refresh operation. The refresh timer includes a voltage regulator, a ring oscillator and a counter. The voltage regulator generates a bias voltage having positive temperature characteristics. The ring oscillator varies an oscillation cycle of a pulse signal according to the bias voltage. The counter counts a prescribed number of pulse signals and generates a refresh signal for executing refresh operation. The semiconductor memory device thus varies the refresh cycle according to a temperature change, and executes refresh operation with an appropriate refresh cycle.

摘要翻译： 半导体存储器件包括用于确定自刷新操作的刷新周期的刷新定时器。 刷新定时器包括电压调节器，环形振荡器和计数器。 电压调节器产生具有正温度特性的偏置电压。 环形振荡器根据偏置电压来改变脉冲信号的振荡周期。 计数器对规定数量的脉冲信号进行计数，并产生用于执行刷新操作的刷新信号。 因此，半导体存储器件根据温度变化而改变刷新周期，并且以适当的刷新周期执行刷新操作。

公开(公告)号：US06873563B2

公开(公告)日：2005-03-29

申请号：US10390886

申请日：2003-03-19

申请人： Makoto Suwa ,  Junko Matsumoto ,  Tadaaki Yamauchi ,  Takeo Okamoto ,  Tetsuichiro Ichiguchi ,  Hideki Yonetani ,  Tsutomu Nagasawa ,  Zengcheng Tian

发明人： Makoto Suwa ,  Junko Matsumoto ,  Tadaaki Yamauchi ,  Takeo Okamoto ,  Tetsuichiro Ichiguchi ,  Hideki Yonetani ,  Tsutomu Nagasawa ,  Zengcheng Tian

IPC分类号： H01L27/04 ,  G11C5/00 ,  G11C5/02 ,  G11C5/06 ,  G11C8/00 ,  G11C11/34 ,  G11C11/401 ,  G11C11/406 ,  G11C11/407 ,  G11C11/409 ,  H01L21/822 ,  H01L23/50 ,  H01L27/10 ,  H02J1/00

CPC分类号： G11C5/025 ,  G11C7/1045 ,  G11C8/10 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4093 ,  G11C2207/105 ,  G11C2211/4061 ,  H01L2224/32145 ,  H01L2924/01019 ,  H01L2924/01037 ,  H01L2924/01068 ,  H01L2924/01087 ,  H01L2924/13091 ,  H01L2924/00

摘要： Data pad regions are arranged in four divided regions of a semiconductor memory chip of a rectangular shape, respectively, and data pads are selectively utilized in each of the four divided regions in accordance with a word structure. Thus, it is possible to implement a semiconductor memory chip capable of being assembled in both a single chip package and a multi chip package.

摘要翻译： 数据焊盘区域分别布置在矩形的半导体存储器芯片的四个分割区域中，并且根据字结构在四个划分的区域中的每一个中选择性地使用数据焊盘。 因此，可以实现能够组装在单个芯片封装和多芯片封装中的半导体存储器芯片。

公开(公告)号：US06954103B2

公开(公告)日：2005-10-11

申请号：US10427968

申请日：2003-05-02

申请人： Tadaaki Yamauchi ,  Junko Matsumoto ,  Takeo Okamoto ,  Makoto Suwa ,  Tetsuichiro Ichiguchi ,  Hideki Yonetani ,  Tsutomu Nagasawa ,  Zengcheng Tian

发明人： Tadaaki Yamauchi ,  Junko Matsumoto ,  Takeo Okamoto ,  Makoto Suwa ,  Tetsuichiro Ichiguchi ,  Hideki Yonetani ,  Tsutomu Nagasawa ,  Zengcheng Tian

IPC分类号： H01L27/04 ,  G11C5/14 ,  G11C11/407 ,  G11C11/4074 ,  H01L21/822 ,  G05F1/46

CPC分类号： G11C11/4074 ,  G11C5/14

摘要： A manner of generating internal voltages such as a high voltage, an intermediate voltage and an internal power supply voltage is switched in accordance with a power supply level setting signal. When the voltage level of an external power supply voltage is low, a current drive transistor receiving an output of a comparing circuit and an auxiliary drive transistor are forcedly set in a conductive state, and external power supply voltage is transmitted on an internal power supply line. At this time, the comparing operation of the comparing circuit is stopped. When the level of the external power supply voltage is high, the comparing circuit is activated down convert the external power supply voltage for generating a peripheral power supply voltage on the internal power supply line.

摘要翻译： 根据电源电平设定信号切换产生高电压，中间电压和内部电源电压等内部电压的方式。 当外部电源电压的电压低时，接收比较电路和辅助驱动晶体管的输出的电流驱动晶体管被强制设定在导通状态，外部电源电压在内部电源线 。 此时，比较电路的比较动作停止。 当外部电源电压为高电平时，比较电路被激活，转换外部电源电压以产生内部电源线上的外围电源电压。

公开(公告)号：US06775177B2

公开(公告)日：2004-08-10

申请号：US10298648

申请日：2002-11-19

申请人： Takeo Okamoto ,  Tetsuichiro Ichiguchi ,  Hideki Yonetani ,  Tsutomu Nagasawa ,  Makoto Suwa ,  Zengcheng Tian ,  Tadaaki Yamauchi ,  Junko Matsumoto

发明人： Takeo Okamoto ,  Tetsuichiro Ichiguchi ,  Hideki Yonetani ,  Tsutomu Nagasawa ,  Makoto Suwa ,  Zengcheng Tian ,  Tadaaki Yamauchi ,  Junko Matsumoto

IPC分类号： G11C1124

CPC分类号： G11C11/405 ,  G11C7/1045 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4087

摘要： A row address decoder of a semiconductor memory device generates internal row address signals RAD and /RAD by switching most significant bit and least significant bit of row address signals RA and /RA that correspond to address signals A0 to A11, respectively. In a twin cell mode, the least significant bits RAD and /RAD of the internal row address signals corresponding to the most significant bits RA and /RA of the row address signal that are not used are selected simultaneously by row address decoder, and two adjacent word lines are activated simultaneously. Consequently, the configuration of memory cell in the semiconductor memory device can electrically be switched from the normal single memory cell type to the twin memory cell type.

摘要翻译： 通过切换行地址信号RA <0:11>和/ RA的最高有效位和最低有效位，半导体存储器件的行地址解码器产生内部行地址信号RAD <0:11>和/ RAD <0:11> 分别对应于地址信号A0至A11的<0:11>。 在双胞模式中，对应于不是行地址信号的最高有效位RA 11和/ RA 11的内部行地址信号的最低有效位RAD <0>和/ RAD <0> 使用的同时由行地址解码器选择，并且两个相邻的字线同时被激活。 因此，半导体存储器件中的存储单元的配置可以从正常的单个存储器单元类型切换到双存储单元类型。

公开(公告)号：US06784718B2

公开(公告)日：2004-08-31

申请号：US10231132

申请日：2002-08-30

申请人： Takeo Okamoto ,  Tadaaki Yamauchi ,  Shinichi Jinbo ,  Makoto Suwa ,  Junko Matsumoto

发明人： Takeo Okamoto ,  Tadaaki Yamauchi ,  Shinichi Jinbo ,  Makoto Suwa ,  Junko Matsumoto

IPC分类号： H03L500

CPC分类号： G11C7/1087 ,  G11C5/147 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222

摘要： An input circuit includes a gate circuit receiving an output power supply voltage that determines the logic level of an input signal or a comparison circuit receiving an input signal and a reference voltage depending on the output power supply voltage supplied from a pad different from a power supply pad for an output circuit. Even if the output power supply voltage varies to cause the input signal to change, whether the input signal is at H level or L level can accurately be determined and an internal signal is generated correctly

摘要翻译： 输入电路包括：门电路，其接收决定输入信号的逻辑电平的输出电源电压或者接收输入信号的比较电路，以及取决于从不同于电源的焊盘提供的输出电源电压的基准电压 用于输出电路的焊盘。 即使输出电源电压变化，导致输入信号变化，输入信号是否处于H电平或L电平，可以准确地确定内部信号是否正确生成

公开(公告)号：USRE35613E

公开(公告)日：1997-09-23

申请号：US496569

申请日：1995-06-29

申请人： Kenichi Yasuda ,  Makoto Suwa ,  Shigeru Mori

发明人： Kenichi Yasuda ,  Makoto Suwa ,  Shigeru Mori

IPC分类号： H01L27/02 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/10805 ,  H01L27/0218 ,  H01L27/105

摘要： A semiconductor memory device includes a first conductivity type well in a first conductivity type semiconductor substrate surrounded by a second conductivity type well, one of a memory cell and an external input circuit arranged on the first conductivity type well and the other disposed outside the second conductivity type well. A predetermined power supply voltage is applied to the second conductivity type well and the first conductivity type well is connected to ground. In the structure, charge carriers injected from the external input circuit are absorbed in the second conductivity type well. As a result, the charge carriers are prevented from reaching the memory cell and destroying data stored therein. Therefore, it is possible to miniaturize transistors and increase integration density of dynamic random access memory devices without degrading the source to drain dielectric strength.

摘要翻译： 半导体存储器件包括第一导电类型的半导体衬底中的第一导电类型的阱，该第一导电类型的半导体衬底由第二导电类型阱围绕，存储单元和布置在第一导电类型阱上的外部输入电路之一，另一个位于第二导电类型 类型很好。 对第二导电类型阱施加预定的电源电压，并且将第一导电类型阱连接到地。 在该结构中，从外部输入电路注入的电荷载流子被吸收在第二导电型阱中。 结果，防止电荷载体到达存储单元并破坏其中存储的数据。 因此，可以使晶体管小型化并提高动态随机存取存储器件的集成密度，而不会使源极降低介电强度。

公开(公告)号：US5357478A

公开(公告)日：1994-10-18

申请号：US767332

申请日：1991-09-30

申请人： Shigeru Kikuda ,  Shigeru Mori ,  Yoshikazu Morooka ,  Hiroshi Miyamoto ,  Makoto Suwa ,  Mitsuya Kinoshita

发明人： Shigeru Kikuda ,  Shigeru Mori ,  Yoshikazu Morooka ,  Hiroshi Miyamoto ,  Makoto Suwa ,  Mitsuya Kinoshita

IPC分类号： H01L21/822 ,  G11C5/02 ,  G11C11/401 ,  H01L27/04 ,  H01L27/10 ,  G11C8/00

CPC分类号： G11C5/025

摘要： A plurality of sub chips are formed on a chip. An input/output buffer region is arranged around the plurality of sub chips. Each sub chip includes a sub chip control circuit region and a plurality of memory cell array blocks. Each memory cell array block includes a memory cell array region, a row decoder and control circuit region, a sense amplifier region and an input/output latch region.

摘要翻译： 在芯片上形成多个子芯片。 输入/输出缓冲区布置在多个子芯片周围。 每个子芯片包括子芯片控制电路区域和多个存储单元阵列块。 每个存储单元阵列块包括存储单元阵列区域，行解码器和控制电路区域，读出放大器区域和输入/输出锁存区域。