公开(公告)号：US07998808B2

公开(公告)日：2011-08-16

申请号：US12409077

申请日：2009-03-23

申请人： Vijay Viswanathan ,  Dev Alok Girdhar ,  Timothy Henson ,  David Paul Jones

发明人： Vijay Viswanathan ,  Dev Alok Girdhar ,  Timothy Henson ,  David Paul Jones

IPC分类号： H01L21/8242 ,  H01L21/20 ,  H01L21/76

CPC分类号： H01L29/7813 ,  H01L21/2815 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734

摘要： A process for fabrication of a semiconductor device that includes forming a first trench in a semiconductor body, forming spaced spacers in the first trench, and forming a narrower second trench at the bottom of the first trench using the spacers as a mask.

摘要翻译： 一种制造半导体器件的方法，包括在半导体本体中形成第一沟槽，在第一沟槽中形成间隔开的间隔物，并且使用间隔物作为掩模，在第一沟槽的底部形成较窄的第二沟槽。

公开(公告)号：US20090263952A1

公开(公告)日：2009-10-22

申请号：US12409077

申请日：2009-03-23

申请人： Vijay Viswanathan ,  Dev Alok Girdhar ,  Timothy Henson ,  David Paul Jones

发明人： Vijay Viswanathan ,  Dev Alok Girdhar ,  Timothy Henson ,  David Paul Jones

IPC分类号： H01L21/44

CPC分类号： H01L29/7813 ,  H01L21/2815 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734

摘要： A process for fabrication of a semiconductor device that includes forming a first trench in a semiconductor body, forming spaced spacers in the first trench, and forming a narrower second trench at the bottom of the first trench using the spacers as a mask.

摘要翻译： 一种半导体器件的制造方法，其包括在半导体本体中形成第一沟槽，在第一沟槽中形成间隔开的间隔物，并且使用间隔物作为掩模，在第一沟槽的底部形成较窄的第二沟槽。

公开(公告)号：US07465986B2

公开(公告)日：2008-12-16

申请号：US11211268

申请日：2005-08-25

申请人： Dev Alok Girdhar ,  Ling Ma ,  Steven T. Peake ,  David Paul Jones

发明人： Dev Alok Girdhar ,  Ling Ma ,  Steven T. Peake ,  David Paul Jones

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/861

摘要： A power semiconductor device includes a plurality of trenches formed within a semiconductor body, each trench including one or more electrodes formed therein. In particular, according to embodiments of the invention, the plurality of trenches of a semiconductor device may include one or more gate electrodes, may include one or more gate electrodes or one or more source electrodes, or may include a combination of both gate and source electrodes formed therein. The trenches and electrodes may have varying depths within the semiconductor body.

摘要翻译： 功率半导体器件包括形成在半导体本体内的多个沟槽，每个沟槽包括形成在其中的一个或多个电极。 具体地，根据本发明的实施例，半导体器件的多个沟槽可以包括一个或多个栅电极，可以包括一个或多个栅电极或一个或多个源电极，或者可以包括栅极和源极的组合 电极形成在其中。 沟槽和电极在半导体本体内可能具有不同的深度。

公开(公告)号：US08860194B2

公开(公告)日：2014-10-14

申请号：US13666854

申请日：2012-11-01

申请人： Ling Ma ,  Andrew N. Sawle ,  David Paul Jones ,  Timothy D. Henson ,  Niraj Ranjan ,  Vijay Viswanathan ,  Omar Hassen

发明人： Ling Ma ,  Andrew N. Sawle ,  David Paul Jones ,  Timothy D. Henson ,  Niraj Ranjan ,  Vijay Viswanathan ,  Omar Hassen

IPC分类号： H01L23/495

CPC分类号： H01L25/18 ,  H01L25/072 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/13091 ,  H01L2924/16251 ,  H02M3/1588 ,  Y02B70/1466 ,  H01L2924/00

摘要： One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.

摘要翻译： 一个示例性的公开的实施例包括包括垂直导通控制晶体管和垂直导通同步晶体管的半导体封装。 垂直传导控制晶体管可以包括控制源，控制栅极和控制漏极，其都可从底表面接近，从而使电和直接表面安装到支撑表面。 垂直导通同步晶体管可以包括顶表面上的同步漏极，其可以连接到耦合到支撑表面的导电夹子。 导电夹子也可以热耦合到控制晶体管。 因此，晶体管的所有端子容易通过支撑表面接近，并且诸如降压转换器电源相的功率电路可以通过支撑表面的迹线来实现。 可选地，驱动器IC可以集成到封装中，并且散热器可以附接到导电夹子。

公开(公告)号：US20140118032A1

公开(公告)日：2014-05-01

申请号：US13666854

申请日：2012-11-01

申请人： Ling Ma ,  Andrew N. Sawle ,  David Paul Jones ,  Timothy D. Henson ,  Niraj Ranjan ,  Vijay Viswanathan ,  Omar Hassen

发明人： Ling Ma ,  Andrew N. Sawle ,  David Paul Jones ,  Timothy D. Henson ,  Niraj Ranjan ,  Vijay Viswanathan ,  Omar Hassen

IPC分类号： H02M3/155

CPC分类号： H01L25/18 ,  H01L25/072 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/13091 ,  H01L2924/16251 ,  H02M3/1588 ,  Y02B70/1466 ,  H01L2924/00

摘要： One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.

摘要翻译： 一个示例性的公开的实施例包括包括垂直导通控制晶体管和垂直导通同步晶体管的半导体封装。 垂直传导控制晶体管可以包括控制源，控制栅极和控制漏极，其都可从底表面接近，从而使电和直接表面安装到支撑表面。 垂直导通同步晶体管可以包括顶表面上的同步漏极，其可连接到耦合到支撑表面的导电夹子。 导电夹子也可以热耦合到控制晶体管。 因此，晶体管的所有端子容易通过支撑表面接近，并且诸如降压转换器电源相的功率电路可以通过支撑表面的迹线来实现。 可选地，驱动器IC可以集成到封装中，并且散热器可以附接到导电夹子。

公开(公告)号：US08844516B2

公开(公告)日：2014-09-30

申请号：US13144998

申请日：2010-01-25

申请人： David Paul Jones ,  Reginald Geraint Brown

发明人： David Paul Jones ,  Reginald Geraint Brown

IPC分类号： F24J2/42 ,  F24D11/00 ,  F24D11/02 ,  F24D5/12 ,  F24D5/00

CPC分类号： F24D11/0264 ,  F24D5/005 ,  F24D5/12 ,  F24D11/007 ,  F24D11/009 ,  F24D11/0285 ,  F24D2200/12 ,  F24D2200/14 ,  Y02B10/20 ,  Y02B10/70 ,  Y02B30/12 ,  Y02B30/125 ,  Y02B30/52

摘要： This relates to a heating device including a solar energy collector, the solar energy collector transferring collected solar energy to outside air. First collector panels are used to heat outside air which heated air is led to a heater, for example a space heater. Second collector panels are used to transfer solar energy to air led to a heat exchanger of a heat pump. The heat pump transfers the extracted heat to heat storage. The stored heat is added to the air coming from the first collector panels if the temperature of the air coming from the first collector panels is below a predetermined temperature.

摘要翻译： 这涉及一种包括太阳能收集器的加热装置，太阳能收集器将收集的太阳能转移到外部空气。 第一收集器板用于加热外部空气，将加热的空气引导到加热器，例如空间加热器。 第二个收集器板用于将太阳能转移到导致热泵热交换器的空气中。 热泵将提取的热量转移到储热。 如果来自第一收集器板的空气的温度低于预定温度，则将储存的热量添加到来自第一收集器板的空气中。

公开(公告)号：US08791525B2

公开(公告)日：2014-07-29

申请号：US12036718

申请日：2008-02-25

申请人： Robert Montgomery ,  Hugo Burke ,  Philip Parsonage ,  Susan Johns ,  David Paul Jones

发明人： Robert Montgomery ,  Hugo Burke ,  Philip Parsonage ,  Susan Johns ,  David Paul Jones

IPC分类号： H01L29/76

CPC分类号： H01L24/11 ,  H01L21/56 ,  H01L24/02 ,  H01L24/10 ,  H01L24/13 ,  H01L29/41775 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2224/0401 ,  H01L2224/11019 ,  H01L2224/11466 ,  H01L2224/11831 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/05494 ,  H01L2924/13091 ,  H01L2924/00

摘要： A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.

摘要翻译： 一种功率半导体器件及其制造方法，其包括在其有源区上的薄金属层和厚金属层的堆叠。

公开(公告)号：US07456470B2

公开(公告)日：2008-11-25

申请号：US11238207

申请日：2005-09-29

申请人： David Paul Jones

发明人： David Paul Jones

IPC分类号： H01L27/108

CPC分类号： H01L29/781 ,  H01L29/417 ,  H01L29/41741 ,  H01L29/42368 ,  H01L29/66734

摘要： A top drain MOSgated device has its drain on the top of semiconductor die and its source on the bottom of the die substrate. Parallel spaced trenches extend from the die top surface through a drift region, a channel region and terminate on the substrate region. The bottoms of each trench receive a silicide conductor to short the substrate source to channel regions. The silicide conductors are then insulated at their top surfaces and gate electrodes are placed in the same trenches as those receiving the channel/source short.

摘要翻译： 顶漏MOS器件的漏极位于半导体管芯的顶部，其源极在管芯基板的底部。 平行隔开的沟槽从模具顶表面延伸穿过漂移区域，沟道区域并终止在衬底区域上。 每个沟槽的底部接收硅化物导体以将衬底源短路至沟道区。 然后，硅化物导体在其顶表面处被绝缘，并且栅电极被放置在与接收沟道/源短的沟槽相同的沟槽中。

公开(公告)号：US07238985B2

公开(公告)日：2007-07-03

申请号：US10911170

申请日：2004-08-04

申请人： David Paul Jones ,  Robert P. Haase

发明人： David Paul Jones ,  Robert P. Haase

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00 ,  H01L31/117

CPC分类号： H01L29/66431 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/7781 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/7827

摘要： A MOSgated trench device has a reduced on resistance by forming a less than about a 13 nm thick strained SiGe layer on the silicon surface of the trenches and forming a thin (30 nm or less) layer of epitaxially deposited silicon on the SiGe layer which epi layer is converted to a gate oxide layer. The conduction channel formed by the SiGe layer is permanently strained to increase its mobility particularly hole mobility.

摘要翻译： MOS沟槽器件通过在沟槽的硅表面上形成小于约13nm厚的应变SiGe层，并且在SiGe层上形成薄（30nm或更小）的外延沉积硅的薄层，其外延 层被转换成栅极氧化物层。 由SiGe层形成的导电通道永久地应变以增加其迁移率，特别是空穴迁移率。

公开(公告)号：US07691708B2

公开(公告)日：2010-04-06

申请号：US11804184

申请日：2007-05-17

申请人： David Paul Jones ,  Robert P. Haase

发明人： David Paul Jones ,  Robert P. Haase

IPC分类号： H01L21/336

CPC分类号： H01L29/66431 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/7781 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/7827

摘要： A MOSgated trench device has a reduced on resistance by forming a less than about a 13 nm thick strained SiGe layer on the silicon surface of the trenches and forming a thin (30 nm or less) layer of epitaxially deposited silicon on the SiGe layer which epi layer is converted to a gate oxide layer. The conduction channel formed by the SiGe layer is permanently strained to increase its mobility particularly hole mobility.

摘要翻译： MOS沟槽器件通过在沟槽的硅表面上形成小于约13nm厚的应变SiGe层，并且在SiGe层上形成薄（30nm或更小）的外延沉积硅的薄层，其外延 层被转换成栅极氧化物层。 由SiGe层形成的导电通道永久地应变以增加其迁移率，特别是空穴迁移率。