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    On-chip sensor array for temperature management in integrated circuits
    1.
    发明授权
    On-chip sensor array for temperature management in integrated circuits 有权
    用于集成电路中温度管理的片上传感器阵列

    公开(公告)号：US07800879B2

    公开(公告)日：2010-09-21

    申请号：US11460459

    申请日：2006-07-27

    Applicant: Vivian Ryan

    Inventor： Vivian Ryan

    IPC: H01L21/00

    CPC classification number: G05D23/20 ,  G05D23/1928

    Abstract: Embodiments of the invention provide methods and apparatus for managing temperature in integrated circuits. In accordance with an aspect of the invention, an integrated circuit comprises a monitored region defined by three or more edges. What is more, the integrated circuit comprises at least two temperature sensors for each of the three or more edges. The temperature sensors are arranged along the three or more edges such that each edge has substantially the same arrangement of temperature sensors. Thermal management of the integrated circuit may be accomplished by modifying functional aspects of the integrated circuit in response to measurements provided by the temperature sensors.

    Abstract translation: 本发明的实施例提供了用于管理集成电路中的温度的方法和装置。 根据本发明的一个方面，集成电路包括由三个或更多个边缘限定的监视区域。 此外，集成电路包括用于三个或更多个边缘中的每一个的至少两个温度传感器。 温度传感器沿着三个或更多个边缘布置，使得每个边缘具有基本相同的温度传感器布置。 集成电路的热管理可以通过响应于由温度传感器提供的测量来修改集成电路的功能方面来实现。

    Lateral double diffused MOS transistors
    2.
    发明授权
    Lateral double diffused MOS transistors 失效
    横向双扩散MOS晶体管

    公开(公告)号：US07573097B2

    公开(公告)日：2009-08-11

    申请号：US10981175

    申请日：2004-11-03

    Applicant: John C. Desko ,  Roger A. Fratti ,  Vivian Ryan

    Inventor： John C. Desko ,  Roger A. Fratti ,  Vivian Ryan

    IPC: H01L29/417 ,  H01L29/423

    CPC classification number: H01L29/7835 ,  H01L23/4824 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The specification describes an improved mechanical electrode structure for MOS transistor devices with elongated runners. It recognizes that shrinking the geometry increases the likelihood of mechanical failure of comb electrode geometries. The mechanical integrity of a comb electrode is improved by interconnecting the electrode fingers in a cross-connected grid. In one embodiment, the transistor device is interconnected with gate fingers on a lower metaliization level, typically the first level metal, with the drain interconnected at a higher metal level. That allows the drain fingers to be cross-connected with a vertical separation between drain and gate comb electrodes. The cross-connect members may be further stabilized by adding beam extensions to the cross-connect members. The beam extensions may be anchored in an interlevel dielectric layer for additional support.

    Abstract translation: 本说明书描述了具有细长流道的用于MOS晶体管器件的改进的机械电极结构。 它认识到缩小几何形状增加了梳状电极几何形状的机械故障的可能性。 梳状电极的机械完整性通过将电极指互连在一个交叉连接的网格中来改进。 在一个实施例中，晶体管器件与较低的金属化级别（通常为第一级金属）与栅极指状物互连，漏极互连在较高的金属水平。 这允许漏极指与电极和门梳电极之间的垂直间隔交叉连接。 交叉连接构件可以通过向交叉连接构件添加梁延伸而进一步稳定。 光束延伸部可以锚定在层间电介质层中用于额外的支撑。

    Metallization performance in electronic devices
    5.
    发明授权
    Metallization performance in electronic devices 有权
    电子设备的金属化性能

    公开(公告)号：US07339274B2

    公开(公告)日：2008-03-04

    申请号：US10919591

    申请日：2004-08-17

    Applicant: John C. Desko, Jr. ,  Bailey R. Jones ,  Sean Lian ,  Simon John Molloy ,  Vivian Ryan

    Inventor： John C. Desko, Jr. ,  Bailey R. Jones ,  Sean Lian ,  Simon John Molloy ,  Vivian Ryan

    IPC: H01L21/283

    CPC classification number: H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Phenomena such as electromigration and stress-induced migration occurring in metal interconnects of devices such as integrated circuits are inhibited by use of underlying non-planarities. Thus the material underlying the interconnect is formed to have non-planarities typically of at least 0.02 μm in height and advantageously within 100 μm of another such non-planarity. Such non-planarities, it is contemplated, reduce grain boundary movement in the overlying interconnect with a concomitant reduction in void aggregation.

    Abstract translation: 诸如集成电路的器件的金属互连中发生的诸如电迁移和应力诱发迁移的现象通过使用下面的非平面性被抑制。 因此，互连下面的材料形成为具有通常在高度上通常为至少0.02μm的非平坦度，并且有利地在另一个这样的非平面性的100μm之内。 可以预期的是，这种非平面性减少了上覆互连中的晶界运动，伴随着空隙聚集的降低。

    Semiconductor device having a dummy conductive via and a method of manufacture therefor
    6.
    发明授权
    Semiconductor device having a dummy conductive via and a method of manufacture therefor 有权
    具有虚拟导电通孔的半导体器件及其制造方法

    公开(公告)号：US07157365B2

    公开(公告)日：2007-01-02

    申请号：US10842139

    申请日：2004-05-10

    Applicant: Vivian Ryan

    Inventor： Vivian Ryan

    IPC: H01L21/4763

    CPC classification number: H01L21/76838 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. In one aspect, the present invention provides a semiconductor device having a dielectric layer located over a conductive feature and a conductive via located within the dielectric layer and contacting the conductive feature. The semiconductor device, among other elements, may further include a dummy conductive via located proximate the conductive via and contacting the conductive feature. One of the intents of the dummy conductive via is to attempt to trap vacancies associated with the conductive feature or the conductive via.

    Abstract translation: 本发明提供一种半导体器件及其制造方法以及包括该半导体器件的集成电路。 在一个方面，本发明提供一种半导体器件，其具有位于导电特征之上的电介质层和位于电介质层内并与导电特征接触的导电通孔。 除了其它元件之外，半导体器件还可以包括位于导电通孔附近并接触导电特征的虚拟导电通孔。 虚拟导电通孔的意图之一是尝试捕获与导电特征或导电通孔相关联的空位。

    Stress migration test structure and method therefor
    8.
    发明授权
    Stress migration test structure and method therefor 有权
    应力迁移试验结构及其方法

    公开(公告)号：US06747445B2

    公开(公告)日：2004-06-08

    申请号：US10007904

    申请日：2001-10-31

    Applicant: H. Scott Fetterman ,  Vivian Ryan

    Inventor： H. Scott Fetterman ,  Vivian Ryan

    IPC: G01N2724

    CPC classification number: H01L22/34 ,  G01R31/2858 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: A stress migration test structure is provided that can be used to detect stress migration defects in traces or conductors of integrated circuits. The stress migration test structure can be placed between die areas on a wafer, or on a die. On the die, a stress migration test structure can be placed in otherwise unused areas of a die such as between bond pads and the periphery of a die, in a layer beneath bond pads, in a region between the bond pads and the perimeter of standard area for circuit layout, or in regions in more than one level of the integrated circuit. The stress migration test structure may also be placed within the standard area for circuit layout and used, with some additional circuitry, as a stress migration test structure on an integrated circuit once the die is packaged. Obtaining information from the impedance segments of a stress migration test structure can be accomplished employing either a mechanical stepping or an electrical stepping technique.

    Abstract translation: 提供了可用于检测集成电路的迹线或导体中的应力迁移缺陷的应力迁移测试结构。 应力迁移测试结构可以放置在晶片上的模具区域或模具之间。 在模具上，应力迁移测试结构可以放置在管芯的其他未使用的区域中，例如在接合焊盘和管芯的外围之间，在接合焊盘下方的层中，在接合焊盘和标准的周边之间的区域中 电路布局区域，或集成电路多个级别的区域。 应力迁移测试结构也可以放置在用于电路布局的标准区域内，并且使用一些额外的电路作为封装芯片时的集成电路上的应力迁移测试结构。 从应力迁移测试结构的阻抗段获取信息可以采用机械步进或电动步进技术来实现。

    Bond pad for a flip chip package, and method of forming the same
    9.
    发明授权
    Bond pad for a flip chip package, and method of forming the same 有权
    用于倒装芯片封装的焊盘，及其形成方法

    公开(公告)号：US06187658B1

    公开(公告)日：2001-02-13

    申请号：US09503814

    申请日：2000-02-15

    Applicant: Sailesh Chittipeddi ,  Vivian Ryan

    Inventor： Sailesh Chittipeddi ,  Vivian Ryan

    IPC: H01L2144

    CPC classification number: H01L24/02 ,  H01L2224/0401 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14

    Abstract: A bond pad support structure is located beneath a bond pad on an integrated circuit. The bond pad support structure includes a first bond pad support layer at least partly located below the bond pad. The first bond pad support layer has a plurality of radial patterns with at least one space between the radial patterns. The radial patterns may be, for example, straight lines having approximately uniform thickness. Alternatively, the radial patterns may be triangles, each of which has an apex pointing to the center of a region below the bond pad. The radial patterns may have a plurality of different lengths. A second bond pad support layer is located on the first bond pad support layer. The second bond pad support layer fills at least a portion of the space between the radial patterns.

    Abstract translation: 接合焊盘支撑结构位于集成电路上的接合焊盘下方。 接合焊盘支撑结构包括至少部分地位于接合焊盘下方的第一接合焊盘支撑层。 第一接合焊盘支撑层具有多个径向图案，其具有在径向图案之间的至少一个空间。 径向图案可以是例如具有近似均匀厚度的直线。 或者，径向图案可以是三角形，每个三角形具有指向接合垫下方的区域的中心的顶点。 径向图案可以具有多个不同的长度。 第二接合焊盘支撑层位于第一接合焊盘支撑层上。 第二接合垫支撑层填充径向图案之间的空间的至少一部分。

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