公开(公告)号：US06346436B1

公开(公告)日：2002-02-12

申请号：US09493627

申请日：2000-01-28

申请人： Yasumori Fukushima ,  Tohru Ueda ,  Kunio Kamimura

发明人： Yasumori Fukushima ,  Tohru Ueda ,  Kunio Kamimura

IPC分类号： H01L2100

CPC分类号： B82Y20/00 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/66439 ,  H01L33/06 ,  H01L33/08 ,  H01S5/341 ,  Y10S438/962

摘要： A nanometer-size quantum thin line is formed on a semiconductor substrate of a Si substrate or the like by means of the general film forming technique, lithographic technique and etching technique. By opportunely using the conventional film forming technique, photolithographic technique and etching technique, a second oxide film that extends in the perpendicular direction is formed on an Si substrate. Then, by removing the second oxide film that extends in the perpendicular direction, a second nitride film located below the film and a first oxide film located below the film by etching, a groove for exposing the Si substrate is formed. Then, a Si thin line is made to epitaxially grow on the exposed portion of the Si substrate. The quantum thin line is thus formed without using any special fine processing technique. The width of the groove can be accurately controlled in nanometers by controlling the film thickness of the second oxide film that is formed by oxidizing the surface of the second nitride film.

摘要翻译： 通过一般的成膜技术，光刻技术和蚀刻技术，在Si衬底等的半导体衬底上形成纳米尺寸量子细线。 通过适当地使用传统的成膜技术，光刻技术和蚀刻技术，在Si衬底上形成沿垂直方向延伸的第二氧化膜。 然后，通过除去沿垂直方向延伸的第二氧化物膜，通过蚀刻位于膜下方的第二氮化物膜和位于膜下方的第一氧化物膜，形成用于暴露Si衬底的沟槽。 然后，使Si细线在Si衬底的暴露部分上外延生长。 因此在不使用任何特殊的精细加工技术的情况下形成量子细线。 通过控制通过氧化第二氮化物膜的表面而形成的第二氧化膜的膜厚，能够以纳米的形式精确地控制槽的宽度。

公开(公告)号：US6090666A

公开(公告)日：2000-07-18

申请号：US163552

申请日：1998-09-30

申请人： Tohru Ueda ,  Kenta Nakamura ,  Yasumori Fukushima

发明人： Tohru Ueda ,  Kenta Nakamura ,  Yasumori Fukushima

IPC分类号： H01L21/8247 ,  G11C16/10 ,  H01L21/20 ,  H01L21/205 ,  H01L27/115 ,  H01L29/06 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L21/02381 ,  B82Y10/00 ,  G11C16/10 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02601 ,  H01L21/0262 ,  H01L21/02667 ,  H01L29/7888 ,  G11C2216/06

摘要： There are provided a method for fabricating semiconductor nanocrystals which are highly controllable and less variable in density and size, as well as a semiconductor memory device which, with the use of the semiconductor nanocrystals, allows thickness of a insulating film between nanocrystals and channel region to be easily controlled and involves less variations in characteristics such as threshold and programming performance, and which is fast reprogrammable and has nonvolatility. Under a low pressure below atmospheric pressure, an amorphous silicon thin film 3 is deposited on a tunnel insulating film 2 formed on a silicon substrate 1. After the deposition of the amorphous silicon thin film 3, the amorphous silicon thin film 3 is heat treated at a temperature not lower than the deposition temperature of the amorphous silicon thin film 3 in an atmosphere of helium gas having no oxidizability, by which a plurality of spherical nanocrystals 4 with a diameter of 18 nm or less are formed on the tunnel insulating film 2 so as to be spaced from one another. The plurality of nanocrystals 4 are used as the floating gate of a semiconductor memory device.

摘要翻译： 提供了一种用于制造高度可控且密度和尺寸变化不大的半导体纳米晶体的方法，以及半导体存储器件，其使用半导体纳米晶体允许纳米晶体和沟道区之间的绝缘膜的厚度 易于控制，并且在诸如阈值和编程性能之类的特性方面的变化较小，并且其是快速可重新编程且具有非易失性的。 在低于大气压的低压下，在形成在硅衬底1上的隧道绝缘膜2上沉积非晶硅薄膜3.在沉积非晶硅薄膜3之后，非晶硅薄膜3被热处理 因此，在隧道绝缘膜2上形成直径为18nm以下的多个球状纳米晶体4，在不具有氧化性的氦气的气氛中，不低于非晶硅薄膜3的沉积温度的温度 以便彼此间隔开。 多个纳米晶体4用作半导体存储器件的浮置栅极。

公开(公告)号：US6013922A

公开(公告)日：2000-01-11

申请号：US85020

申请日：1998-05-28

申请人： Tohru Ueda ,  Kenta Nakamura ,  Yasumori Fukushima

发明人： Tohru Ueda ,  Kenta Nakamura ,  Yasumori Fukushima

IPC分类号： H01L21/8247 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L27/10 ,  H01L29/66 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L29/167 ,  H01L29/207 ,  H01L29/227

CPC分类号： H01L21/2022 ,  B82Y10/00 ,  H01L29/66757 ,  H01L29/7888 ,  H01L28/84

摘要： A semiconductor storage element has a source region, a drain region, and a channel region connecting the source region with the drain region, which each are formed on an insulation film of a substrate. A gate insulation film is formed between the channel region and a gate electrode. The source region, the drain region, and the channel region consist of an aggregate of spherical grains which are arranged two-dimensionally on the insulation film and connected with one another such that the adjacent spherical grains are conductive to one another. The channel region contains at least one carrier trap region provided at a location other than an electric path thereof.

摘要翻译： 半导体存储元件具有源极区域，漏极区域和连接源极区域与漏极区域的沟道区域，其各自形成在衬底的绝缘膜上。 在沟道区和栅电极之间形成栅极绝缘膜。 源极区域，漏极区域和沟道区域由二维地布置在绝缘膜上并且彼此连接使得相邻的球形颗粒彼此导电的球形颗粒聚集体组成。 沟道区域包含至少一个载流子陷阱区域，该区域设置在除电路以外的位置。

公开(公告)号：US06337259B1

公开(公告)日：2002-01-08

申请号：US09579440

申请日：2000-05-26

申请人： Tohru Ueda ,  Yasumori Fukushima ,  Yoshinori Higami

发明人： Tohru Ueda ,  Yasumori Fukushima ,  Yoshinori Higami

IPC分类号： H01L21322

CPC分类号： H01L29/66757 ,  H01L21/3226 ,  H01L29/78675

摘要： An amorphous silicon film is deposited on a quartz substrate, and a metal of Ni is introduced into the amorphous silicon film so that the amorphous silicon film is crystallized. Phosphorus is ion-implanted with an oxide pattern used as a mask. A heating process is performed in a nitrogen atmosphere, by which Ni is gettered. A heating process is performed in an O2 atmosphere, by which Ni is gettered into the oxide. Like this, by performing the first gettering in a non-oxidative atmosphere, the Ni concentration can be reduced to such a level that oxidation does not cause any increase of irregularities or occurrence of pinholes. Thus, in a second gettering, enough oxidation can be effected without minding any increase of irregularities and occurrence of pinholes, so that the Ni concentration can be reduced to an extremely low level. Also, a high-quality crystalline silicon film free from surface irregularities and pinholes can be obtained.

摘要翻译： 将非晶硅膜沉积在石英衬底上，将Ni的金属引入到非晶硅膜中，使得非晶硅膜结晶化。 用作为掩模的氧化物图案离子注入磷。 在氮气气氛中进行加热处理，Ni被吸收。 在O2气氛中进行加热处理，通过该加热处理将Ni吸收到氧化物中。 像这样，通过在非氧化性气氛中进行第一吸气，可以将Ni浓度降低到氧化不引起不规则性增加或针孔发生的程度。 因此，在第二吸气中，可以实现足够的氧化，而不会引起不规则性的增加和针孔的发生，使得Ni浓度可以降低到非常低的水平。 此外，可以获得没有表面凹凸和针孔的高品质结晶硅膜。

公开(公告)号：US06326311B1

公开(公告)日：2001-12-04

申请号：US09277761

申请日：1999-03-29

申请人： Tohru Ueda ,  Yasumori Fukushima ,  Fumitoshi Yasuo

发明人： Tohru Ueda ,  Yasumori Fukushima ,  Fumitoshi Yasuo

IPC分类号： H01L2972

CPC分类号： B82Y10/00 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/66439 ,  Y10S438/962

摘要： There is provided a microstructure producing method capable of achieving satisfactory uniformity and reproducibility of the growth position, size and density of a minute particle or thin line and materializing a semiconductor device which can reduce the cost through simple processes without using any special microfabrication technique and has superior characteristics appropriate for mass-production with high yield and high productivity as well as a semiconductor device employing the microstructure. An oxide film 12 having a region 12a of a great film thickness and a region 12b of a small film thickness are formed on the surface of a semiconductor substrate 11. Next, a microstructure that is a thin line 15 made of silicon Si is selectively formed only on the surface of the small-film-thickness region 12b of the oxide film 12.

摘要翻译： 提供了一种微结构制造方法，其能够实现微粒或细线的生长位置，尺寸和密度的均匀性和再现性，并且实现半导体器件，其可以通过简单的工艺降低成本而不使用任何特殊的微细加工技术，并且具有 适用于大批量生产且具有高产率和高生产率的优异特性以及采用微结构的半导体器件。 在半导体基板11的表面上形成具有膜厚度大的区域12a和薄膜厚度小的区域12b的氧化物膜12.接下来，选择形成由硅Si制成的细线15的微观结构 仅在氧化膜12的小膜厚度区域12b的表面上。

公开(公告)号：US06310376B1

公开(公告)日：2001-10-30

申请号：US09165800

申请日：1998-10-02

申请人： Tohru Ueda ,  Kenta Nakamura ,  Yasumori Fukushima

发明人： Tohru Ueda ,  Kenta Nakamura ,  Yasumori Fukushima

IPC分类号： H01L29788

CPC分类号： B82Y10/00 ,  H01L29/7883 ,  H01L29/7887 ,  H01L29/7888

摘要： There is provided is a semiconductor storage device that can reduce a dispersion in characteristics such as a threshold voltage and a writing performance and has a low consumption power and a non-volatility. There are included a source region 9 and a drain region 10 formed on a silicon substrate 1, a channel region 3a located between the source and drain regions 9 and 10, a gate electrode 8 that is formed above the channel region 3a and controls a channel current flowing through the channel region 3a, and a control gate insulating film 7, a floating gate 6 and a tunnel insulating film 4 that are arranged in order from the gate electrode 8 side between the channel region 3a and the gate electrode 8. The floating gate 6 is comprised of a plurality of crystal grains 6a linearly discretely arranged substantially parallel to the surface of the channel region 3a.

摘要翻译： 提供了可以降低诸如阈值电压和写入性能等特性的色散并具有低消耗功率和非挥发性的半导体存储装置。 包括形成在硅衬底1上的源极区9和漏极区10，位于源极和漏极区9和10之间的沟道区3a，形成在沟道区3a上方的栅极8并控制沟道 流过沟道区域3a的电流以及从沟道区域3a和栅电极8之间的栅电极8侧依次排列的控制栅绝缘膜7，浮栅6和隧道绝缘膜4。 栅极6由基本上平行于沟道区域3a的表面线性离散布置的多个晶粒6a组成。

公开(公告)号：US6103600A

公开(公告)日：2000-08-15

申请号：US159645

申请日：1998-09-24

申请人： Tohru Ueda ,  Yasumori Fukushima ,  Kenta Nakamura

发明人： Tohru Ueda ,  Yasumori Fukushima ,  Kenta Nakamura

IPC分类号： H01L21/8247 ,  H01L21/20 ,  H01L21/205 ,  H01L21/28 ,  H01L21/762 ,  H01L27/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/76 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L33/34 ,  H01L33/44 ,  H01L21/00 ,  H01L21/31 ,  H01L21/469 ,  H01L21/84

CPC分类号： B82Y10/00 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/28273 ,  H01L21/76202 ,  H01L29/7613 ,  Y10S438/962

摘要： A quantum dot and quantum fine wire forming method is provided which can allow control of the position for crystalline particle growth and enables formation of particles with high uniformity in size and density and with high reproducibility. After an Si substrate is formed with a step by a dry etching method, an SiO.sub.2 film is formed on the surface of the substrate. The interior of a reaction chamber is evacuated to a vacuum of 10.sup.-8 Torr, and then an Si.sub.2 H.sub.6 gas is introduced into the reaction chamber to flow therein so that Si crystal particles (quantum dots) are formed along the step. The step is formed by conventional photolithography and dry etching; therefore, the position for quantum dot growth can be easily controlled. By controlling the rate and time period of gas flow and the temperature of the substrate it is possible to form quantum fine wires, and to control the size of quantum dots and/or thickness of quantum fine wires. In this way, high uniformity in quantum dot and/or quantum fine wire size/thickness and density can be realized with high reproducibility. Further, low cost production, high yield, and high productivity can be achieved without use of any special fine processing technique.

摘要翻译： 提供了量子点和量子细线形成方法，其可以控制晶粒生长的位置，并且能够形成尺寸和密度均匀性高的重复性高的颗粒。 在通过干蚀刻方法形成Si衬底之后，在衬底的表面上形成SiO 2膜。 将反应室的内部抽真空至10-8托的真空，然后将Si 2 H 6气体引入反应室中流动，从而沿着该步骤形成Si晶体颗粒（量子点）。 该步骤通过常规光刻和干蚀刻形成; 因此，可以容易地控制量子点生长的位置。 通过控制气流的速率和时间以及衬底的温度，可以形成量子细线，并且控制量子细丝的量子点的尺寸和/或厚度。 以这种方式，可以以高再现性实现量子点和/或量子细线尺寸/厚度和密度的高均匀性。 此外，可以实现低成本生产，高产率和高生产率，而不使用任何特殊的精细加工技术。

公开(公告)号：US20140078458A1

公开(公告)日：2014-03-20

申请号：US14118587

申请日：2012-06-15

申请人： Yasumori Fukushima

发明人： Yasumori Fukushima

IPC分类号： H01L27/12 ,  G02F1/1362

CPC分类号： H01L27/1218 ,  G02F1/133305 ,  G02F1/133345 ,  G02F1/1362 ,  Y10T428/2495

摘要： The thickness of a rear surface-side inorganic film (9) formed from the same material as that of each of front surface-side inorganic films (11, 13, and 16) and provided at a rear surface side of a resin substrate (10) having a heat resistance is set in a predetermined range with respect to the total thickness of the front surface-side inorganic films (11, 13, and 16) so that the curvature diameter calculated based on the linear elastic modulus, the coefficient of linear expansion, and the thickness of the resin substrate (10); the linear elastic moduli, the coefficients of linear expansion, and the total thickness of the front surface-side inorganic films (11, 13, and 16); and the linear elastic modulus, the coefficient of linear expansion, and the thickness of the rear surface-side inorganic film (9) is 20 mm or more or −20 mm or less.

摘要翻译： 由与前表面侧无机膜（11,13和16）相同的材料形成并设置在树脂基板（10）的背面侧的后表面侧无机膜（9）的厚度 ）相对于前表面侧无机膜（11,13和16）的总厚度设定在预定范围内，使得基于线性弹性模量计算的曲率直径，线性系数 膨胀和树脂基板（10）的厚度; 线性弹性模量，线膨胀系数和前表面侧无机膜（11,13和16）的总厚度; 并且后表面侧无机膜（9）的线弹性模量，线膨胀系数和厚度为20mm以上或-20mm以下。

公开(公告)号：US20130100392A1

公开(公告)日：2013-04-25

申请号：US13807040

申请日：2011-06-24

申请人： Yasumori Fukushima

发明人： Yasumori Fukushima

IPC分类号： G02F1/133 ,  G02F1/1333

CPC分类号： G02F1/13306 ,  G02F1/1333 ,  G09F9/30 ,  G09F9/301

摘要： A flexible display device (100) according to the present invention includes a display panel (10), a circuit board (30), a circuit part (32), and a housing (20). The display panel, the circuit board, and the housing have flexibility at least along a first direction which is perpendicular to the plane of the display panel. A length 2a of the circuit part along a second direction which is parallel to the plane of the display panel, a thickness b of the circuit part along the first direction, a distance d between the bottom face and the upper face of the housing or between the bottom face of the housing and a lower face of the display panel, and a radius of curvature r of the bottom face of the housing when the housing is curved to a maximum extent along the first direction satisfy the relationship a≦[d2−b2+2·r·(d−b)](1/2). According to the present invention, a highly flexible electronic device or display device can be provided by using circuit parts of appropriate sizes, without unnecessarily increasing the device thickness.

摘要翻译： 根据本发明的柔性显示装置（100）包括显示面板（10），电路板（30），电路部分（32）和壳体（20）。 显示面板，电路板和壳体至少沿着垂直于显示面板的平面的第一方向具有柔性。 沿着与显示面板的平面平行的第二方向的电路部分的长度2a，电路部分沿着第一方向的厚度b，底面和壳体的上表面之间的距离d，或者 当壳体沿着第一方向弯曲到最大程度时，壳体的底面和显示面板的下表面以及壳体的底面的曲率半径r满足关系a @ [d2-b2 + 2·r·（db）]（1/2）。 根据本发明，可以通过使用适当尺寸的电路部件来提供高度灵活的电子装置或显示装置，而不必增加装置厚度。

公开(公告)号：US20120326264A1

公开(公告)日：2012-12-27

申请号：US13497807

申请日：2010-05-18

申请人： Yasumori Fukushima ,  Yutaka Takafuji ,  Kenshi Tada

发明人： Yasumori Fukushima ,  Yutaka Takafuji ,  Kenshi Tada

IPC分类号： H01L21/58 ,  H01L25/00

CPC分类号： H01L27/1266 ,  H01L27/1218 ,  H01L29/66772

摘要： A method of fabricating a semiconductor device of the present invention includes the steps of forming a single crystal semiconductor device, attaching the single crystal semiconductor device on a substrate, forming a TFT on a glass substrate, and electrically connecting the single crystal semiconductor device and the TFT. In the step of forming a single crystal semiconductor device, an alignment mark is provided at the single crystal semiconductor device. In the step of attaching a single crystal semiconductor device, the single crystal semiconductor device is positioned and attached on the glass substrate based on the machining accuracy of an attachment device. In the step of forming a TFT, the TFT is positioned and provided on the glass substrate based on the alignment mark provided at the single crystal semiconductor device.

摘要翻译： 制造本发明的半导体器件的方法包括以下步骤：形成单晶半导体器件，将单晶半导体器件安装在衬底上，在玻璃衬底上形成TFT，并将单晶半导体器件和 TFT。 在形成单晶半导体器件的步骤中，在单晶半导体器件上设置对准标记。 在安装单晶半导体器件的步骤中，单晶半导体器件基于安装器件的加工精度被定位并附着在玻璃基板上。 在形成TFT的步骤中，基于设置在单晶半导体器件上的对准标记，将TFT设置在玻璃基板上。