公开(公告)号：US06898851B2

公开(公告)日：2005-05-31

申请号：US10717718

申请日：2003-11-21

申请人： Yasutaka Nishioka ,  Junjiro Sakai ,  Shingo Tomohisa ,  Susumu Matsumoto ,  Fumio Iwamoto ,  Michinari Yamanaka

发明人： Yasutaka Nishioka ,  Junjiro Sakai ,  Shingo Tomohisa ,  Susumu Matsumoto ,  Fumio Iwamoto ,  Michinari Yamanaka

IPC分类号： H01K3/10 ,  H01L21/768 ,  H05K3/10

CPC分类号： H01L21/76808 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

摘要： It is an object to provide a semiconductor device having a buried multilayer wiring structure in which generation of a resolution defect of a resist pattern is suppressed and generation of a defective wiring caused by the resolution defect is reduced. After a via hole (7) reaching an etching stopper film (4) is formed, annealing is carried out at 300 to 400° C. with the via hole (7) opened. As an annealing method, it is possible to use both a method using a hot plate and a method using a heat treating furnace. In order to suppress an influence on a lower wiring (20) which has been manufactured, heating is carried out for a short time of approximately 5 to 10 minutes by using the hot plate. Consequently, a by-product staying in an interface of an upper protective film (6) and an interlayer dielectric film (5) having a low dielectric constant and a by-product staying in an interface of the etching stopper film (4) and the interlayer dielectric film (5) having a low dielectric constant are discharged so that an amount of the residual by-product can be decreased.

摘要翻译： 本发明的目的是提供一种具有掩埋多层布线结构的半导体器件，其中抗蚀剂图案的分辨率缺陷的产生被抑制，并且由分辨率缺陷引起的缺陷布线的产生减少。 在形成到达蚀刻停止膜（4）的通孔（7）之后，在通孔（7）打开的情况下，在300〜400℃进行退火。 作为退火方法，可以使用使用热板的方法和使用热处理炉的方法。 为了抑制对制造的下布线（20）的影响，通过使用热板进行约5〜10分钟的短时间的加热。 因此，残留在上部保护膜（6）和具有低介电常数的副产物残留在蚀刻阻挡膜（4）的界面上的层间电介质膜（5）的界面中的副产物和 排出具有低介电常数的层间绝缘膜（5），从而可以减少残留副产物的量。

公开(公告)号：US07022619B2

公开(公告)日：2006-04-04

申请号：US10395182

申请日：2003-03-25

申请人： Michinari Yamanaka ,  Hiroshi Yuasa ,  Tetsuo Satake ,  Etsuyoshi Kobori ,  Takeshi Yamashita ,  Susumu Matsumoto

发明人： Michinari Yamanaka ,  Hiroshi Yuasa ,  Tetsuo Satake ,  Etsuyoshi Kobori ,  Takeshi Yamashita ,  Susumu Matsumoto

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/4763

CPC分类号： H01L21/76831 ,  H01L21/76808 ,  H01L21/76826

摘要： After a hole is formed in a low dielectric constant film on a substrate, a protective film is formed on the wall surface of the hole or an electron acceptor is caused to be adsorbed by or implanted in the low dielectric constant film exposed at the wall surface of the hole. Otherwise, resist residue is left on the wall surface of the hole. Then, a resist pattern having an opening corresponding to a wire formation region including a region formed with the hole is formed by using a chemically amplified resist.

公开(公告)号：US07605085B2

公开(公告)日：2009-10-20

申请号：US11532603

申请日：2006-09-18

申请人： Kazuo Tomita ,  Keiji Hashimoto ,  Yasutaka Nishioka ,  Susumu Matsumoto ,  Mitsuru Sekiguchi ,  Akihisa Iwasaki

发明人： Kazuo Tomita ,  Keiji Hashimoto ,  Yasutaka Nishioka ,  Susumu Matsumoto ,  Mitsuru Sekiguchi ,  Akihisa Iwasaki

IPC分类号： H01L21/311

CPC分类号： H01L23/522 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： First wirings and first dummy wirings are formed in a p-SiOC film formed on a substrate. A p-SiOC film is formed, and a cap film is formed on the p-SiOC film. A dual damascene wiring, including vias connected to the first wirings and the second wirings, is formed in the cap film and the p-SiOC film 22. Dummy vias are formed on the periphery of isolated vias.

摘要翻译： 在基板上形成的p-SiOC膜中形成第一布线和第一伪布线。 形成p-SiOC膜，在p-SiOC膜上形成盖膜。 在盖膜和p-SiOC膜22中形成包括连接到第一布线和第二布线的通孔的双镶嵌布线。在隔离的通孔的周边上形成有通孔。

公开(公告)号：US20060163730A1

公开(公告)日：2006-07-27

申请号：US10520816

申请日：2004-04-07

申请人： Susumu Matsumoto ,  Mitsuru Sekiguchi ,  Yasutaka Nishioka ,  Kazuo Tomita ,  Akihisa Iwasaki ,  Keiji Hashimoto

发明人： Susumu Matsumoto ,  Mitsuru Sekiguchi ,  Yasutaka Nishioka ,  Kazuo Tomita ,  Akihisa Iwasaki ,  Keiji Hashimoto

IPC分类号： H01L23/52

CPC分类号： H01L21/76801 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/0274 ,  H01L21/3144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76829 ,  H01L21/76835

摘要： A first nitrogen-containing insulating film is formed under a low dielectric constant film, in which a via hole is formed, with a first nitrogen-non-containing insulating film interposed between the first nitrogen-containing insulating film and the low dielectric constant film. A second nitrogen-containing insulating film is formed over the low dielectric constant film with a second nitrogen-non-containing insulating film interposed therebetween.

摘要翻译： 在第一含氮绝缘膜和低介电常数膜之间插入第一含氮不含绝缘膜的低介电常数膜形成第一含氮绝缘膜，其中形成通孔。 在低介电常数膜上形成第二含氮绝缘膜，其间插入第二含氮不含绝缘膜。

公开(公告)号：US20050035457A1

公开(公告)日：2005-02-17

申请号：US10791751

申请日：2004-03-04

申请人： Kazuo Tomita ,  Keiji Hashimoto ,  Yasutaka Nishioka ,  Susumu Matsumoto ,  Mitsuru Sekiguchi ,  Akihisa Iwasaki

发明人： Kazuo Tomita ,  Keiji Hashimoto ,  Yasutaka Nishioka ,  Susumu Matsumoto ,  Mitsuru Sekiguchi ,  Akihisa Iwasaki

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/02

CPC分类号： H01L23/522 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： First wirings and first dummy wirings are in a p-SiOC film on a substrate. A p-SiOC film is formed, and a cap film is formed on the p-SiOC film. A dual damascene wiring, including vias connected to the first wirings and the second wirings, is formed in the cap film and the p-SiOC film 22. Dummy vias are formed on the periphery of isolated vias.

摘要翻译： 第一布线和第一虚拟布线在基板上的p-SiOC膜中。 形成p-SiOC膜，在p-SiOC膜上形成盖膜。 在盖膜和p-SiOC膜22中形成包括连接到第一布线和第二布线的通孔的双镶嵌布线。在隔离的通孔的周边上形成有通孔。

公开(公告)号：US20130217915A1

公开(公告)日：2013-08-22

申请号：US13882265

申请日：2011-10-27

申请人： Yuta Nakazawa ,  Susumu Matsumoto ,  Tomoaki Kobayashi ,  Tatsuhiko Kurakami

发明人： Yuta Nakazawa ,  Susumu Matsumoto ,  Tomoaki Kobayashi ,  Tatsuhiko Kurakami

IPC分类号： C07C51/16

CPC分类号： C07C51/16 ,  B01J23/002 ,  B01J23/8877 ,  B01J27/199 ,  B01J35/0006 ,  B01J35/04 ,  B01J37/0036 ,  B01J37/0045 ,  B01J37/0244 ,  B01J2523/00 ,  C07C51/235 ,  C07C57/04 ,  B01J2523/17 ,  B01J2523/53 ,  B01J2523/55 ,  B01J2523/68

摘要： The present invention relates to a method for producing acrylic acid through vapor-phase contact oxidation of acrolein, wherein a reactor tube is divided into at least two catalyst layers, and catalysts having a higher activity are charged in the reactor tube sequentially toward an outlet port side from a material source gas inlet port side for a reaction therein to give acrylic acid, and wherein a catalyst activity-controlling method is a method comprising: a step of mixing a molybdenum-containing compound, a vanadium-containing compound, a copper-containing compound and an antimony-containing compound with water, then drying and calcining a resulting mixture, in which a catalytically-active element composition is kept constant but material source compounds are made to vary in type to give composite metal oxides having a different activity.

摘要翻译： 本发明涉及一种通过丙烯醛的气相接触氧化制备丙烯酸的方法，其中将反应器管分成至少两个催化剂层，并且具有较高活性的催化剂依次连接到反应器管的出口 一边从材料源气体入口侧进行反应，得到丙烯酸，其中催化剂活性控制方法是一种方法，包括：将含钼化合物，含钒化合物，铜 - 然后干燥和煅烧所得混合物，其中催化活性元素组合物保持恒定，但是使材料源化合物的类型变化，得到具有不同活性的复合金属氧化物。

公开(公告)号：US08378462B2

公开(公告)日：2013-02-19

申请号：US13214759

申请日：2011-08-22

申请人： Susumu Matsumoto

发明人： Susumu Matsumoto

IPC分类号： H01L29/40 ,  H01L23/053 ,  H01L23/12 ,  H01L23/48 ,  H01L23/52 ,  H01L23/02

CPC分类号： H01L21/76898 ,  H01L21/76831 ,  H01L23/481 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/0401

摘要： A semiconductor device includes a semiconductor substrate including a first surface serving as an element formation surface, and a second surface opposite to the first surface; a through-via penetrating the semiconductor substrate; an insulating via coating film formed between a sidewall of the through-via and the semiconductor substrate; and an insulating protective film formed on the second surface of the semiconductor substrate. The via coating film and the protective film are different insulating films from each other.

摘要翻译： 半导体器件包括：半导体衬底，包括用作元件形成表面的第一表面和与第一表面相对的第二表面; 穿透半导体衬底的通孔; 形成在贯通孔的侧壁和半导体基板之间的绝缘通路涂膜; 以及形成在半导体衬底的第二表面上的绝缘保护膜。 通孔涂膜和保护膜是彼此不同的绝缘膜。

公开(公告)号：US20070108614A1

公开(公告)日：2007-05-17

申请号：US11620976

申请日：2007-01-08

申请人： Koji Eriguchi ,  Susumu Matsumoto

发明人： Koji Eriguchi ,  Susumu Matsumoto

IPC分类号： H01L23/48

CPC分类号： H01L21/76838

摘要： At least a laminate of a gate insulating film 6 and a gate electrode 7 and an active region 13 are formed on a silicon substrate 1, and an underlying interlayer insulating film 10 is further formed. Then, a conductor 11a connected to the gate electrode 7, and a conductor 11b that is a dummy conductor and is connected to the active region 13 are formed simultaneously on the underlying interlayer insulating film 10. Thereafter, an interlayer insulating film 12 is formed on the underlying interlayer insulating film 10 by a plasma process. At this time, charging current from a plasma 14 is emitted through the conductor 11b, which is a dummy conductor.

摘要翻译： 至少在硅衬底1上形成栅极绝缘膜6和栅电极7以及有源区13的层叠体，并进一步形成下层层间绝缘膜10。 然后，在下面的层间绝缘膜10上同时形成连接到栅电极7的导体11a和作为虚拟导体并连接到有源区13的导体11b。 此后，通过等离子体处理在下层层间绝缘膜10上形成层间绝缘膜12。 此时，来自等离子体14的充电电流通过作为虚拟导体的导体11b发出。

公开(公告)号：USD361213S

公开(公告)日：1995-08-15

申请号：US18170

申请日：1994-01-31

申请人： Katsuhiro Tokutake ,  Susumu Matsumoto

设计人： Katsuhiro Tokutake ,  Susumu Matsumoto

公开(公告)号：US5405800A

公开(公告)日：1995-04-11

申请号：US274048

申请日：1994-07-12

申请人： Hisashi Ogawa ,  Susumu Matsumoto ,  Shin Hashimoto ,  Hiroyuki Umimoto

发明人： Hisashi Ogawa ,  Susumu Matsumoto ,  Shin Hashimoto ,  Hiroyuki Umimoto

IPC分类号： H01L27/108 ,  H01L21/70

CPC分类号： H01L27/10808

摘要： A method of fabricating a semiconductor memory device on a semiconductor substrate is disclosed. A gate electrode that becomes a word line, a bit line, and a charge-storage electrode are formed in a memory cell array region of a semiconductor substrate. A capacitor insulator layer and a plate electrode are formed in that order. Then, a BPSG film is formed in the memory cell array region and in the peripheral circuit region. A resist pattern is formed on the BPSG film, leaving the memory cell array region exposed. Using the resist pattern thus formed as a mask, an etching treatment is applied to remove an upper surface portion of the BPSG film lying within the memory cell array region by a given amount. After the resist pattern is removed, the BPSG film is heated in order that it reflows to planarize.

摘要翻译： 公开了一种在半导体衬底上制造半导体存储器件的方法。 在半导体衬底的存储单元阵列区域中形成成为字线，位线和电荷存储电极的栅电极。 依次形成电容器绝缘体层和平板电极。 然后，在存储单元阵列区域和外围电路区域中形成BPSG膜。 在BPSG膜上形成抗蚀剂图案，使存储单元阵列区域暴露。 使用如此形成的抗蚀剂图案作为掩模，进行蚀刻处理以将存在于存储单元阵列区域内的BPSG膜的上表面部分除去给定量。 在除去抗蚀剂图案之后，加热BPSG膜，使其回流平坦化。