公开(公告)号：US06898851B2

公开(公告)日：2005-05-31

申请号：US10717718

申请日：2003-11-21

申请人： Yasutaka Nishioka ,  Junjiro Sakai ,  Shingo Tomohisa ,  Susumu Matsumoto ,  Fumio Iwamoto ,  Michinari Yamanaka

发明人： Yasutaka Nishioka ,  Junjiro Sakai ,  Shingo Tomohisa ,  Susumu Matsumoto ,  Fumio Iwamoto ,  Michinari Yamanaka

IPC分类号： H01K3/10 ,  H01L21/768 ,  H05K3/10

CPC分类号： H01L21/76808 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

摘要： It is an object to provide a semiconductor device having a buried multilayer wiring structure in which generation of a resolution defect of a resist pattern is suppressed and generation of a defective wiring caused by the resolution defect is reduced. After a via hole (7) reaching an etching stopper film (4) is formed, annealing is carried out at 300 to 400° C. with the via hole (7) opened. As an annealing method, it is possible to use both a method using a hot plate and a method using a heat treating furnace. In order to suppress an influence on a lower wiring (20) which has been manufactured, heating is carried out for a short time of approximately 5 to 10 minutes by using the hot plate. Consequently, a by-product staying in an interface of an upper protective film (6) and an interlayer dielectric film (5) having a low dielectric constant and a by-product staying in an interface of the etching stopper film (4) and the interlayer dielectric film (5) having a low dielectric constant are discharged so that an amount of the residual by-product can be decreased.

摘要翻译： 本发明的目的是提供一种具有掩埋多层布线结构的半导体器件，其中抗蚀剂图案的分辨率缺陷的产生被抑制，并且由分辨率缺陷引起的缺陷布线的产生减少。 在形成到达蚀刻停止膜（4）的通孔（7）之后，在通孔（7）打开的情况下，在300〜400℃进行退火。 作为退火方法，可以使用使用热板的方法和使用热处理炉的方法。 为了抑制对制造的下布线（20）的影响，通过使用热板进行约5〜10分钟的短时间的加热。 因此，残留在上部保护膜（6）和具有低介电常数的副产物残留在蚀刻阻挡膜（4）的界面上的层间电介质膜（5）的界面中的副产物和 排出具有低介电常数的层间绝缘膜（5），从而可以减少残留副产物的量。

公开(公告)号：US20050035457A1

公开(公告)日：2005-02-17

申请号：US10791751

申请日：2004-03-04

申请人： Kazuo Tomita ,  Keiji Hashimoto ,  Yasutaka Nishioka ,  Susumu Matsumoto ,  Mitsuru Sekiguchi ,  Akihisa Iwasaki

发明人： Kazuo Tomita ,  Keiji Hashimoto ,  Yasutaka Nishioka ,  Susumu Matsumoto ,  Mitsuru Sekiguchi ,  Akihisa Iwasaki

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/02

CPC分类号： H01L23/522 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： First wirings and first dummy wirings are in a p-SiOC film on a substrate. A p-SiOC film is formed, and a cap film is formed on the p-SiOC film. A dual damascene wiring, including vias connected to the first wirings and the second wirings, is formed in the cap film and the p-SiOC film 22. Dummy vias are formed on the periphery of isolated vias.

摘要翻译： 第一布线和第一虚拟布线在基板上的p-SiOC膜中。 形成p-SiOC膜，在p-SiOC膜上形成盖膜。 在盖膜和p-SiOC膜22中形成包括连接到第一布线和第二布线的通孔的双镶嵌布线。在隔离的通孔的周边上形成有通孔。

公开(公告)号：US07605085B2

公开(公告)日：2009-10-20

申请号：US11532603

申请日：2006-09-18

申请人： Kazuo Tomita ,  Keiji Hashimoto ,  Yasutaka Nishioka ,  Susumu Matsumoto ,  Mitsuru Sekiguchi ,  Akihisa Iwasaki

发明人： Kazuo Tomita ,  Keiji Hashimoto ,  Yasutaka Nishioka ,  Susumu Matsumoto ,  Mitsuru Sekiguchi ,  Akihisa Iwasaki

IPC分类号： H01L21/311

CPC分类号： H01L23/522 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： First wirings and first dummy wirings are formed in a p-SiOC film formed on a substrate. A p-SiOC film is formed, and a cap film is formed on the p-SiOC film. A dual damascene wiring, including vias connected to the first wirings and the second wirings, is formed in the cap film and the p-SiOC film 22. Dummy vias are formed on the periphery of isolated vias.

摘要翻译： 在基板上形成的p-SiOC膜中形成第一布线和第一伪布线。 形成p-SiOC膜，在p-SiOC膜上形成盖膜。 在盖膜和p-SiOC膜22中形成包括连接到第一布线和第二布线的通孔的双镶嵌布线。在隔离的通孔的周边上形成有通孔。

公开(公告)号：US20060163730A1

公开(公告)日：2006-07-27

申请号：US10520816

申请日：2004-04-07

申请人： Susumu Matsumoto ,  Mitsuru Sekiguchi ,  Yasutaka Nishioka ,  Kazuo Tomita ,  Akihisa Iwasaki ,  Keiji Hashimoto

发明人： Susumu Matsumoto ,  Mitsuru Sekiguchi ,  Yasutaka Nishioka ,  Kazuo Tomita ,  Akihisa Iwasaki ,  Keiji Hashimoto

IPC分类号： H01L23/52

CPC分类号： H01L21/76801 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/0274 ,  H01L21/3144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76829 ,  H01L21/76835

摘要： A first nitrogen-containing insulating film is formed under a low dielectric constant film, in which a via hole is formed, with a first nitrogen-non-containing insulating film interposed between the first nitrogen-containing insulating film and the low dielectric constant film. A second nitrogen-containing insulating film is formed over the low dielectric constant film with a second nitrogen-non-containing insulating film interposed therebetween.

摘要翻译： 在第一含氮绝缘膜和低介电常数膜之间插入第一含氮不含绝缘膜的低介电常数膜形成第一含氮绝缘膜，其中形成通孔。 在低介电常数膜上形成第二含氮绝缘膜，其间插入第二含氮不含绝缘膜。

公开(公告)号：US5286605A

公开(公告)日：1994-02-15

申请号：US788378

申请日：1991-11-06

申请人： Yasutaka Nishioka ,  Hiroshi Kawashima ,  Shoji Suzuki

发明人： Yasutaka Nishioka ,  Hiroshi Kawashima ,  Shoji Suzuki

IPC分类号： H01L27/148 ,  G03F7/00 ,  G03F7/09 ,  H01L27/14 ,  H01L31/0216 ,  H01L31/0232 ,  H04N5/335 ,  H04N5/365 ,  H04N5/372 ,  G03F7/26

CPC分类号： H01L27/14685 ,  G03F7/0035 ,  G03F7/094 ,  H01L27/14627 ,  H01L31/02164 ,  H01L31/0232

摘要： In a method for producing a micro lens in a solid-state imaging device, a thermally stable transparent resin layer for forming a planar surface is deposited on a base layer of the solid-state imaging device, a far-ultraviolet sensitive thermoplastic layer is deposited on the transparent layer, a photosensitive resin layer sensitive to light of longer wavelength than the far-ultraviolet sensitive resin layer and highly absorbing far-ultraviolet light is deposited on the far-ultraviolet sensitive resin layer, portions of the photosensitive resin layer are removed, far-ultraviolet light irradiates the resin layers, portions of the far-ultraviolet sensitive resin layers are removed, and portions of the transparent layer are thermally deformed into a desired micro lens shape. Therefore, access to the bonding pad under the transparent resin film can be obtained after the deposition and patterning of the thermoplastic resin film wherein non-uniformities in the thermoplastic resin film are reduced, resulting is a micro lens having high light collection ability and no wavelength sensitivity variations.

摘要翻译： 在固体摄像装置中的微透镜的制造方法中，在固体摄像装置的基底层上淀积形成平坦面的热稳定性透明树脂层，沉积有紫外线敏感的热塑性层 在透明层上，对远紫外线敏感树脂层的波长较长的光敏感的感光性树脂层和高吸收性的远紫外光被沉积在紫外线敏感性树脂层上，去除感光性树脂层的部分， 远紫外线照射树脂层，去除部分紫外线敏感性树脂层，透明层的一部分热变形成所需的微透镜形状。 因此，在热塑性树脂膜中的不均匀性降低的热塑性树脂膜的沉积和图案化之后，可以获得在透明树脂膜下的接合焊盘，导致具有高聚光能力和无波长的微透镜 灵敏度变化。

公开(公告)号：US20100052062A1

公开(公告)日：2010-03-04

申请号：US12502008

申请日：2009-07-13

申请人： Shoichi Fukui ,  Noboru Morimoto ,  Yasutaka Nishioka ,  Junko Izumitani ,  Atsushi Ishii

发明人： Shoichi Fukui ,  Noboru Morimoto ,  Yasutaka Nishioka ,  Junko Izumitani ,  Atsushi Ishii

IPC分类号： H01L27/088 ,  H01L21/28

CPC分类号： H01L23/5329 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/76849 ,  H01L21/76867 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide a manufacturing method of a semiconductor device which can improve the reliability of the semiconductor device. A first insulating film for covering a semiconductor element formed in a semiconductor substrate is formed by a thermal CVD method or the like which has a good embedding property. A second insulating film is formed to cover the first insulating film by a plasma CVD method which has excellent humidity resistance. A plug is formed to penetrate the first insulating film and the second insulating film. A third insulating film comprised of a low-k film having a relatively low dielectric constant is formed over the second insulating film. A wiring is formed in the third insulating film by a damascene technique to be electrically coupled to the plug.

摘要翻译： 提供能提高半导体器件的可靠性的半导体器件的制造方法。 用于覆盖形成在半导体衬底中的半导体元件的第一绝缘膜通过具有良好嵌入特性的热CVD法等形成。 通过等离子体CVD法形成第二绝缘膜以覆盖第一绝缘膜，其具有优异的耐湿性。 形成插塞以穿透第一绝缘膜和第二绝缘膜。 在第二绝缘膜上形成由具有较低介电常数的低k膜构成的第三绝缘膜。 通过镶嵌技术在第三绝缘膜中形成布线以与插头电耦合。

公开(公告)号：US08728853B2

公开(公告)日：2014-05-20

申请号：US13265513

申请日：2009-04-24

申请人： Akie Yutani ,  Yasutaka Nishioka

发明人： Akie Yutani ,  Yasutaka Nishioka

IPC分类号： H01L21/00

CPC分类号： H01L27/14685 ,  H01L27/14603 ,  H01L27/14605 ,  H01L27/14609 ,  H01L27/14612 ,  H01L27/1462 ,  H01L27/14643 ,  H01L27/14689

摘要： By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall. Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating. At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.

摘要翻译： 通过选择性地各向异性地蚀刻形成为覆盖多个光电二极管的堆叠膜和MOS晶体管的栅极电极层，堆叠膜保留在多个光电二极管中的每一个上，以形成较低的抗反射涂层，并且堆叠膜保留在 栅电极层形成侧壁。 使用栅极电极层和侧壁作为掩模，引入杂质以形成MOS晶体管的源极/漏极区域。 在引入杂质之后，至少在较低的抗反射涂层上形成上部抗反射涂层。 蚀刻上部抗反射涂层和下部抗反射涂层中的至少一个，使得两个相应光电二极管上的抗反射涂层的厚度彼此不同。

公开(公告)号：US20120037968A1

公开(公告)日：2012-02-16

申请号：US13265513

申请日：2009-04-24

申请人： Akie Yutani ,  Yasutaka Nishioka

发明人： Akie Yutani ,  Yasutaka Nishioka

IPC分类号： H01L31/02

CPC分类号： H01L27/14685 ,  H01L27/14603 ,  H01L27/14605 ,  H01L27/14609 ,  H01L27/14612 ,  H01L27/1462 ,  H01L27/14643 ,  H01L27/14689

摘要： By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall. Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating. At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.

摘要翻译： 通过选择性地各向异性地蚀刻形成为覆盖多个光电二极管的堆叠膜和MOS晶体管的栅极电极层，堆叠膜保留在多个光电二极管中的每一个上，以形成较低的抗反射涂层，并且堆叠膜保留在 栅电极层形成侧壁。 使用栅极电极层和侧壁作为掩模，引入杂质以形成MOS晶体管的源极/漏极区域。 在引入杂质之后，至少在较低的抗反射涂层上形成上部抗反射涂层。 蚀刻上部抗反射涂层和下部抗反射涂层中的至少一个，使得两个相应光电二极管上的抗反射涂层的厚度彼此不同。

公开(公告)号：US08008730B2

公开(公告)日：2011-08-30

申请号：US12502008

申请日：2009-07-13

申请人： Shoichi Fukui ,  Noboru Morimoto ,  Yasutaka Nishioka ,  Junko Izumitani ,  Atsushi Ishii

发明人： Shoichi Fukui ,  Noboru Morimoto ,  Yasutaka Nishioka ,  Junko Izumitani ,  Atsushi Ishii

IPC分类号： H01L21/02

CPC分类号： H01L23/5329 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/76849 ,  H01L21/76867 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide a manufacturing method of a semiconductor device which can improve the reliability of the semiconductor device. A first insulating film for covering a semiconductor element formed in a semiconductor substrate is formed by a thermal CVD method or the like which has a good embedding property. A second insulating film is formed to cover the first insulating film by a plasma CVD method which has excellent humidity resistance. A plug is formed to penetrate the first insulating film and the second insulating film. A third insulating film comprised of a low-k film having a relatively low dielectric constant is formed over the second insulating film. A wiring is formed in the third insulating film by a damascene technique to be electrically coupled to the plug.

摘要翻译： 提供能提高半导体器件的可靠性的半导体器件的制造方法。 用于覆盖半导体衬底中形成的半导体元件的第一绝缘膜通过具有良好嵌入特性的热CVD法等形成。 通过等离子体CVD法形成第二绝缘膜以覆盖第一绝缘膜，其具有优异的耐湿性。 形成插塞以穿透第一绝缘膜和第二绝缘膜。 在第二绝缘膜上形成由具有较低介电常数的低k膜构成的第三绝缘膜。 通过镶嵌技术在第三绝缘膜中形成布线以与插头电耦合。

公开(公告)号：US06228728B1

公开(公告)日：2001-05-08

申请号：US09243480

申请日：1999-02-03

申请人： Taisuke Furukawa ,  Takumi Nakahata ,  Shigemitsu Maruno ,  Kohei Sugihara ,  Yasutaka Nishioka ,  Satoshi Yamakawa ,  Yasunori Tokuda

发明人： Taisuke Furukawa ,  Takumi Nakahata ,  Shigemitsu Maruno ,  Kohei Sugihara ,  Yasutaka Nishioka ,  Satoshi Yamakawa ,  Yasunori Tokuda

IPC分类号： H01L21336

CPC分类号： H01L29/66628

摘要： According to the inventive method of fabricating a semiconductor device, a silicon substrate is exposed to an oxygen atmosphere of 600° C. to 900° C., for forming silicon oxide films on surfaces of epitaxial silicon layers and those of silicon fragments. Thus, a method of fabricating a semiconductor device capable of preventing electrodes thereof from shorting can be provided.

摘要翻译： 根据制造半导体器件的本发明方法，将硅衬底暴露于600℃至900℃的氧气氛中，以在外延硅层和硅片的表面上形成氧化硅膜。 因此，可以提供一种制造能够防止其电极短路的半导体器件的方法。