利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

75 条记录 (耗时 0.028 秒)

    Electronic device manufacturing method
    4.
    发明授权
    Electronic device manufacturing method 失效
    电子元件制造方法

    公开(公告)号：US06898851B2

    公开(公告)日：2005-05-31

    申请号：US10717718

    申请日：2003-11-21

    申请人： Yasutaka Nishioka ,  Junjiro Sakai ,  Shingo Tomohisa ,  Susumu Matsumoto ,  Fumio Iwamoto ,  Michinari Yamanaka

    发明人： Yasutaka Nishioka ,  Junjiro Sakai ,  Shingo Tomohisa ,  Susumu Matsumoto ,  Fumio Iwamoto ,  Michinari Yamanaka

    IPC分类号： H01K3/10 ,  H01L21/768 ,  H05K3/10

    CPC分类号： H01L21/76808 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

    摘要： It is an object to provide a semiconductor device having a buried multilayer wiring structure in which generation of a resolution defect of a resist pattern is suppressed and generation of a defective wiring caused by the resolution defect is reduced. After a via hole (7) reaching an etching stopper film (4) is formed, annealing is carried out at 300 to 400° C. with the via hole (7) opened. As an annealing method, it is possible to use both a method using a hot plate and a method using a heat treating furnace. In order to suppress an influence on a lower wiring (20) which has been manufactured, heating is carried out for a short time of approximately 5 to 10 minutes by using the hot plate. Consequently, a by-product staying in an interface of an upper protective film (6) and an interlayer dielectric film (5) having a low dielectric constant and a by-product staying in an interface of the etching stopper film (4) and the interlayer dielectric film (5) having a low dielectric constant are discharged so that an amount of the residual by-product can be decreased.

    摘要翻译： 本发明的目的是提供一种具有掩埋多层布线结构的半导体器件，其中抗蚀剂图案的分辨率缺陷的产生被抑制，并且由分辨率缺陷引起的缺陷布线的产生减少。 在形成到达蚀刻停止膜（4）的通孔（7）之后，在通孔（7）打开的情况下，在300〜400℃进行退火。 作为退火方法，可以使用使用热板的方法和使用热处理炉的方法。 为了抑制对制造的下布线（20）的影响，通过使用热板进行约5〜10分钟的短时间的加热。 因此，残留在上部保护膜（6）和具有低介电常数的副产物残留在蚀刻阻挡膜（4）的界面上的层间电介质膜（5）的界面中的副产物和 排出具有低介电常数的层间绝缘膜（5），从而可以减少残留副产物的量。

    Catalyst and Method for Producing Acrylic Acid
    5.
    发明申请
    Catalyst and Method for Producing Acrylic Acid 有权
    催化剂和生产丙烯酸的方法

    公开(公告)号：US20130217915A1

    公开(公告)日：2013-08-22

    申请号：US13882265

    申请日：2011-10-27

    申请人： Yuta Nakazawa ,  Susumu Matsumoto ,  Tomoaki Kobayashi ,  Tatsuhiko Kurakami

    发明人： Yuta Nakazawa ,  Susumu Matsumoto ,  Tomoaki Kobayashi ,  Tatsuhiko Kurakami

    IPC分类号： C07C51/16

    CPC分类号： C07C51/16 ,  B01J23/002 ,  B01J23/8877 ,  B01J27/199 ,  B01J35/0006 ,  B01J35/04 ,  B01J37/0036 ,  B01J37/0045 ,  B01J37/0244 ,  B01J2523/00 ,  C07C51/235 ,  C07C57/04 ,  B01J2523/17 ,  B01J2523/53 ,  B01J2523/55 ,  B01J2523/68

    摘要： The present invention relates to a method for producing acrylic acid through vapor-phase contact oxidation of acrolein, wherein a reactor tube is divided into at least two catalyst layers, and catalysts having a higher activity are charged in the reactor tube sequentially toward an outlet port side from a material source gas inlet port side for a reaction therein to give acrylic acid, and wherein a catalyst activity-controlling method is a method comprising: a step of mixing a molybdenum-containing compound, a vanadium-containing compound, a copper-containing compound and an antimony-containing compound with water, then drying and calcining a resulting mixture, in which a catalytically-active element composition is kept constant but material source compounds are made to vary in type to give composite metal oxides having a different activity.

    摘要翻译： 本发明涉及一种通过丙烯醛的气相接触氧化制备丙烯酸的方法，其中将反应器管分成至少两个催化剂层，并且具有较高活性的催化剂依次连接到反应器管的出口 一边从材料源气体入口侧进行反应，得到丙烯酸，其中催化剂活性控制方法是一种方法，包括：将含钼化合物，含钒化合物，铜 - 然后干燥和煅烧所得混合物，其中催化活性元素组合物保持恒定，但是使材料源化合物的类型变化，得到具有不同活性的复合金属氧化物。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20070108614A1

    公开(公告)日：2007-05-17

    申请号：US11620976

    申请日：2007-01-08

    申请人： Koji Eriguchi ,  Susumu Matsumoto

    发明人： Koji Eriguchi ,  Susumu Matsumoto

    IPC分类号： H01L23/48

    CPC分类号： H01L21/76838

    摘要： At least a laminate of a gate insulating film 6 and a gate electrode 7 and an active region 13 are formed on a silicon substrate 1, and an underlying interlayer insulating film 10 is further formed. Then, a conductor 11a connected to the gate electrode 7, and a conductor 11b that is a dummy conductor and is connected to the active region 13 are formed simultaneously on the underlying interlayer insulating film 10. Thereafter, an interlayer insulating film 12 is formed on the underlying interlayer insulating film 10 by a plasma process. At this time, charging current from a plasma 14 is emitted through the conductor 11b, which is a dummy conductor.

    摘要翻译： 至少在硅衬底1上形成栅极绝缘膜6和栅电极7以及有源区13的层叠体，并进一步形成下层层间绝缘膜10。 然后，在下面的层间绝缘膜10上同时形成连接到栅电极7的导体11a和作为虚拟导体并连接到有源区13的导体11b。 此后，通过等离子体处理在下层层间绝缘膜10上形成层间绝缘膜12。 此时，来自等离子体14的充电电流通过作为虚拟导体的导体11b发出。

    Method of fabricating a semiconductor memory device
    9.
    发明授权
    Method of fabricating a semiconductor memory device 失效
    制造半导体存储器件的方法

    公开(公告)号：US5405800A

    公开(公告)日：1995-04-11

    申请号：US274048

    申请日：1994-07-12

    申请人： Hisashi Ogawa ,  Susumu Matsumoto ,  Shin Hashimoto ,  Hiroyuki Umimoto

    发明人： Hisashi Ogawa ,  Susumu Matsumoto ,  Shin Hashimoto ,  Hiroyuki Umimoto

    IPC分类号： H01L27/108 ,  H01L21/70

    CPC分类号： H01L27/10808

    摘要： A method of fabricating a semiconductor memory device on a semiconductor substrate is disclosed. A gate electrode that becomes a word line, a bit line, and a charge-storage electrode are formed in a memory cell array region of a semiconductor substrate. A capacitor insulator layer and a plate electrode are formed in that order. Then, a BPSG film is formed in the memory cell array region and in the peripheral circuit region. A resist pattern is formed on the BPSG film, leaving the memory cell array region exposed. Using the resist pattern thus formed as a mask, an etching treatment is applied to remove an upper surface portion of the BPSG film lying within the memory cell array region by a given amount. After the resist pattern is removed, the BPSG film is heated in order that it reflows to planarize.

    摘要翻译： 公开了一种在半导体衬底上制造半导体存储器件的方法。 在半导体衬底的存储单元阵列区域中形成成为字线，位线和电荷存储电极的栅电极。 依次形成电容器绝缘体层和平板电极。 然后，在存储单元阵列区域和外围电路区域中形成BPSG膜。 在BPSG膜上形成抗蚀剂图案，使存储单元阵列区域暴露。 使用如此形成的抗蚀剂图案作为掩模，进行蚀刻处理以将存在于存储单元阵列区域内的BPSG膜的上表面部分除去给定量。 在除去抗蚀剂图案之后，加热BPSG膜，使其回流平坦化。

    Thin-film semiconductor device and method of fabricating the same
    10.
    发明授权
    Thin-film semiconductor device and method of fabricating the same 失效
    薄膜半导体器件及其制造方法

    公开(公告)号：US5214296A

    公开(公告)日：1993-05-25

    申请号：US848840

    申请日：1992-03-10

    申请人： Yoshiro Nakata ,  Naoto Matsuo ,  Toshiki Yabu ,  Susumu Matsumoto ,  Shozo Okada

    发明人： Yoshiro Nakata ,  Naoto Matsuo ,  Toshiki Yabu ,  Susumu Matsumoto ,  Shozo Okada

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L29/786

    CPC分类号： H01L29/78642 ,  H01L27/10817

    摘要： A thin-film semiconductor device having a vertical TFT which includes a gate insulating film formed on a sidewall of a throughhole formed in an insulating layer; a thin-film semiconductor layer formed on the gate insulating film; and a gate electrode formed within the insulating layer. The gate electrode, the gate insulating film, and the thin-film semiconductor layer together form a lateral MOS structure. The thin-film semiconductor layer is connected to a bit line at the bottom of the throughhole and to a storage node of a capacitor formed over the switching transistor.

    摘要翻译： 一种具有垂直TFT的薄膜半导体器件，其包括形成在绝缘层中形成的通孔的侧壁上的栅极绝缘膜; 形成在所述栅极绝缘膜上的薄膜半导体层; 以及形成在所述绝缘层内的栅电极。 栅电极，栅极绝缘膜和薄膜半导体层一起形成横向MOS结构。 薄膜半导体层连接到通孔底部的位线和形成在开关晶体管上的电容器的存储节点。