公开(公告)号：US07411806B2

公开(公告)日：2008-08-12

申请号：US11634405

申请日：2006-12-06

申请人： Seiji Funaba ,  Yoji Nishio ,  Kayoko Shibata

发明人： Seiji Funaba ,  Yoji Nishio ,  Kayoko Shibata

IPC分类号： G11C5/06 ,  G11C5/02

CPC分类号： G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C11/4093 ,  G11C2207/105 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19107

摘要： A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.

摘要翻译： 存储器模块具有在板的前表面和后表面上共享总线的多个DRAM（115）。 总线通过通孔（113）从端子（111）连接到带状线（112）的一端，并且带状线的另一端通过通孔（113）连接到另一层中的带状线 孔（119）用于使线路循环。 设置在终端电压端子（VTT）附近的终端电阻器（120）通过通孔连接到另一层中的环形带状线。 DRAM端子通过通孔连接到带状线。 该存储器模块通过连接器安装在其上提供存储器控制器的母板上。 母线的有效特性阻抗与母板线路特性阻抗匹配。

公开(公告)号：US07161820B2

公开(公告)日：2007-01-09

申请号：US10628517

申请日：2003-07-28

申请人： Seiji Funaba ,  Yoji Nishio ,  Kayoko Shibata

发明人： Seiji Funaba ,  Yoji Nishio ,  Kayoko Shibata

IPC分类号： G11C5/00 ,  G11C5/06

CPC分类号： G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C11/4093 ,  G11C2207/105 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19107

摘要： A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.

摘要翻译： 存储器模块具有在板的前表面和后表面上共享总线的多个DRAM（115）。 总线通过通孔（113）从端子（111）连接到带状线（112）的一端，并且带状线的另一端通过通孔（113）连接到另一层中的带状线 孔（119）用于使线路循环。 设置在终端电压端子（VTT）附近的终端电阻器（120）通过通孔连接到另一层中的环形带状线。 DRAM端子通过通孔连接到带状线。 该存储器模块通过连接器安装在其上提供存储器控制器的母板上。 母线的有效特性阻抗与母板线路特性阻抗匹配。

公开(公告)号：US07051225B2

公开(公告)日：2006-05-23

申请号：US10427090

申请日：2003-04-30

申请人： Yoji Nishio ,  Kayoko Shibata ,  Seiji Funaba

发明人： Yoji Nishio ,  Kayoko Shibata ,  Seiji Funaba

IPC分类号： G06F1/04

CPC分类号： G11C7/109 ,  G11C7/1078 ,  G11C7/1093

摘要： Disclosed are a memory command address system and a memory module that can be operated not only for 266 MHzCLK but also for 200 MHzCLK, in which clock timings in the input sections of a PLL, a register, and a DRAM are matched to one another, a DLL (delay locked loop) is provided in the register, the output timing of CA signal from the register is controlled so that the setup time margin and the hold time margin of the CA signal with respect to the clock signal with the additional latency in the DRAM=1.5 or 2.0 are equated to each other, such that clock operation of 266 MHz, for example, is made possible. If both 266 MHz and 200 MHz are used, by taking account of the timing budget, control is made for retarding the timing of the CA signal input to the flip-flop which receives an internal clock signal (intCLK) supplied to the flip-flop for determining the CA signal output timing from the register. Alternatively, control is made for switching between the replica (replical) provided in the register and an output unit associated with the replica, depending on the frequency being used, so as to cope with both frequencies simply by providing one sort of the module and one sort of the register.

摘要翻译： 公开了一种存储器命令地址系统和存储器模块，其不仅可以用于266MHzCLK，而且可以用于200MHzCLK，其中PLL，寄存器和DRAM的输入部分中的时钟定时彼此匹配， 在寄存器中提供DLL（延迟锁定环），控制来自寄存器的CA信号的输出定时，使得CA信号的建立时间余量和保持时间裕度相对于时钟信号具有额外的等待时间 DRAM = 1.5或2.0彼此相等，使得例如266MHz的时钟操作成为可能。 如果使用266MHz和200MHz，通过考虑时序预算，进行控制以延迟输入到触发器的CA信号的定时，该触发器接收提供给触发器的内部时钟信号（intCLK） 用于确定来自寄存器的CA信号输出定时。 或者，根据所使用的频率，进行控制以在寄存器中提供的副本（复制）和与副本相关联的输出单元之间进行切换，从而简单地通过提供一种模块和一个模块来处理两个频率 排序的注册表。

公开(公告)号：US20070081376A1

公开(公告)日：2007-04-12

申请号：US11634405

申请日：2006-12-06

申请人： Seiji Funaba ,  Yoji Nishio ,  Kayoko Shibata

发明人： Seiji Funaba ,  Yoji Nishio ,  Kayoko Shibata

IPC分类号： G11C5/06

CPC分类号： G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C11/4093 ,  G11C2207/105 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19107

摘要： A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.

摘要翻译： 存储器模块具有在板的前表面和后表面上共享总线的多个DRAM（115）。 总线通过通孔（113）从端子（111）连接到带状线（112）的一端，并且带状线的另一端通过通孔（113）连接到另一层中的带状线 孔（119）用于使线路循环。 设置在终端电压端子（VTT）附近的终端电阻器（120）通过通孔连接到另一层中的环形带状线。 DRAM端子通过通孔连接到带状线。 该存储器模块通过连接器安装在其上提供存储器控制器的母板上。 母线的有效特性阻抗与母板线路特性阻抗匹配。

公开(公告)号：US07016212B2

公开(公告)日：2006-03-21

申请号：US10630457

申请日：2003-07-29

申请人： Kayoko Shibata ,  Yoji Nishio ,  Seiji Funaba

发明人： Kayoko Shibata ,  Yoji Nishio ,  Seiji Funaba

IPC分类号： G11C5/06

CPC分类号： H05K1/0246 ,  H05K2201/10022 ,  H05K2201/10159

摘要： A memory module comprises a stab resistor between a pin and one end of a bus. A plurality of memory chips is connected to the bus between both ends thereof. A terminating resistor is connected to the other end of the bus. Stab resistance Rs of the stab resistor and terminating resistance Rterm of the terminating resistor are given by: Rs=(N−1)×Zeffdimm/N, and Rterm=Zeffdimm where N represents the number of the memory modules in a memory system; and Zeffdimm, effective impedance of a memory chip arrangement portion consisting of the bus and the memory chips. In the memory system, the memory modules are connected to a memory controller on a motherboard in a stab connection style. Wiring impedance Zmb of the motherboard is given by: Zmb=(2N−1)×Zeffdimm/N2.

摘要翻译： 存储器模块包括在引脚和总线的一端之间的尖端电阻器。 多个存储器芯片在其两端之间连接到总线。 终端电阻连接到总线的另一端。 尖端电阻的阻抗Rs和终端电阻的终端电阻Rterm由下式给出：<？in-line-formula description =“In-line Formulas”end =“lead”？> Rs =（N-1）xZeffdimm / N和<？in-line-formula description =“In-line Formulas”end =“tail”？> <？in-line-formula description =“In-line Formulas”end =“lead”？> Rterm = Zeffdimm <？in-line-formula description =“在线公式”end =“tail”？>其中N表示存储器系统中的存储器模块的数量; 和Zeffdimm，由总线和存储器芯片组成的存储芯片布置部分的有效阻抗。 在存储器系统中，存储器模块以连接方式连接到主板上的存储器控​​制器。 主板的接线阻抗Zmb由下式给出：<？in-line-formula description =“In-line formula”end =“lead”？> Zmb =（2N-1）xZeffdimm / N < 。<？in-line-formula description =“In-line Formulas”end =“tail”？>

公开(公告)号：US06986072B2

公开(公告)日：2006-01-10

申请号：US10206822

申请日：2002-07-29

申请人： Yoji Nishio ,  Seiji Funaba ,  Kayoko Shibata ,  Toshio Sugano ,  Hiroaki Ikeda ,  Takuo Iizuka ,  Masayuki Sorimachi

发明人： Yoji Nishio ,  Seiji Funaba ,  Kayoko Shibata ,  Toshio Sugano ,  Hiroaki Ikeda ,  Takuo Iizuka ,  Masayuki Sorimachi

IPC分类号： G11C7/08 ,  G06F1/06 ,  G06F1/10

CPC分类号： G11C5/04 ,  G11C5/00 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/222 ,  H03L7/0814

摘要： A maximum value of the number of mounted memory devices is assumed, and a value of an external delay replica is fixed and set. A desired frequency band is divided into a plurality of sub-frequency bands, and delay times of an output buffer and an internal delay replica are switched and used every sub-frequency band, thereby setting an actual maximum value and an actual minimum value to the internal delay replica. A selecting pin can select the delay time in the internal delay replica. Thus, it is possible to sufficiently ensure a set-up time and a hold time of an internal clock signal generated by a delay locked loop circuit in the latch operation in a register within a desired frequency band and with a permittable number of memory devices, irrespective of the frequency level and the number of mounted memory devices.

公开(公告)号：US06707726B2

公开(公告)日：2004-03-16

申请号：US10206823

申请日：2002-07-29

申请人： Yoji Nishio ,  Seiji Funaba ,  Kayoko Shibata ,  Toshio Sugano ,  Hiroaki Ikeda ,  Takuo Iizuka ,  Masayuki Sorimachi

发明人： Yoji Nishio ,  Seiji Funaba ,  Kayoko Shibata ,  Toshio Sugano ,  Hiroaki Ikeda ,  Takuo Iizuka ,  Masayuki Sorimachi

IPC分类号： G11C700

CPC分类号： G11C7/109 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/06 ,  G11C2207/107

摘要： First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of ½ of an external clock signal and an inverse clock thereof. Thus, the command/address signal is decomprossed to a set of signals which temporarily has two times. For example, one of the set of signals has only data contents of an odd-th command/address signal, and the other has only data contents of an even-th command/address signal. Since the set of signals has twice periods of the command/address signal, first and second post-processing flip-flop can latch signals in accordance with an internal clock signal generated by a delay locked loop circuit in a state in which a set-up time and a hold time are sufficiently assured.

摘要翻译： 第一和第二预处理触发器通过具有外部时钟信号的1/2的频率的时钟及其反时钟来锁存输入到寄存器的命令/地址信号。 因此，命令/地址信号被分解成一组暂时具有两次的信号。 例如，该组信号之一仅具有奇数命令/地址信号的数据内容，而另一个仅具有偶数个命令/地址信号的数据内容。 由于该组信号具有两个命令/地址信号的周期，所以第一和第二后处理触发器可以根据由延迟锁定环电路产生的内部时钟信号来锁存信号， 时间和保持时间充分确保。

公开(公告)号：US20060006516A1

公开(公告)日：2006-01-12

申请号：US11176292

申请日：2005-07-08

申请人： Seiji Funaba ,  Yoji Nishio

发明人： Seiji Funaba ,  Yoji Nishio

IPC分类号： H01L23/02

CPC分类号： H01L23/66 ,  G11C5/04 ,  G11C5/063 ,  H01L24/06 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/06136 ,  H01L2224/49171 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device module includes a wiring substrate, a plurality of stacked semiconductor devices and a damping impedance circuit. The plurality of stacked semiconductor devices are provided on the wiring substrate and connected with a signal in a stubless manner, and each of the plurality of stacked semiconductor devices comprises a plurality of semiconductor chips which are stacked. The damping impedance circuit is provided for a transmission path of the signal for an uppermost semiconductor chip as the furthest one, from the wiring substrate, of the plurality of semiconductor chips of a first stacked semiconductor device as one of the plurality of stacked semiconductor devices which is first supplied with the signal.

摘要翻译： 半导体器件模块包括布线基板，多个堆叠半导体器件和阻尼阻抗电路。 多个堆叠的半导体器件设置在布线基板上，并且以简单的方式与信号连接，并且多个堆叠的半导体器件中的每一个包括堆叠的多个半导体芯片。 阻尼阻抗电路被设置为用于作为多个半导体器件中的一个堆叠半导体器件的第一堆叠半导体器件的多个半导体芯片中的最上半个半导体芯片的信号的距离布线基板的最远的信号的传输路径， 首先提供信号。

公开(公告)号：US20050139977A1

公开(公告)日：2005-06-30

申请号：US11019553

申请日：2004-12-23

申请人： Yoji Nishio ,  Seiji Funaba

发明人： Yoji Nishio ,  Seiji Funaba

IPC分类号： H01L23/14 ,  G06F1/18 ,  G06F13/00 ,  G11C5/02 ,  G11C7/00 ,  G11C11/407 ,  H01L21/68 ,  H01L23/02 ,  H01L23/498 ,  H01L23/50 ,  H01L23/66 ,  H01L25/065 ,  H01L25/07 ,  H01L27/108 ,  H05K1/14

CPC分类号： H01L23/66 ,  G06F1/184 ,  G06F1/185 ,  G06F1/186 ,  G11C5/025 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/50 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/0102 ,  H01L2924/01068 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H05K1/141 ,  H01L2924/00

摘要： A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane for the wiring in the Si unit. The wiring topology between a chip set and the COC DRAM is the same for every signal. Accordingly, a memory system enabling a high-speed operation, low power consumption, and large capacity is provided.

摘要翻译： 包括多个堆叠的DRAM芯片的COC DRAM通过使用插入件安装在母板上。 插入器包括Si单元和PCB。 Si单元包括Si基板和布置布线的绝缘层单元。 PCB包括用于Si单元中布线的参考平面。 芯片组和COC DRAM之间的布线结构对于每个信号是相同的。 因此，提供了能够进行高速运转，低功耗，大容量的存储器系统。

公开(公告)号：US06628538B2

公开(公告)日：2003-09-30

申请号：US10105249

申请日：2002-03-26

申请人： Seiji Funaba ,  Yoshinobu Nakagome ,  Masashi Horiguchi ,  Yoji Nishio

发明人： Seiji Funaba ,  Yoshinobu Nakagome ,  Masashi Horiguchi ,  Yoji Nishio

IPC分类号： G11C506

CPC分类号： G11C5/06 ,  G11C5/04 ,  G11C5/063 ,  H01L23/5387 ,  H01L25/065 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06579 ,  H01L2924/01055 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/3011

摘要： A module substrate has a plurality of module data terminal pairs individually provided in association with respective chip data terminals in a plurality of memory chips, and a plurality of module data wirings which respectively connect between the plurality of module data terminal pairs. The plurality of module data wirings are connected to their corresponding chip data terminals and are configured so as to be available as a memory access data bus. In a memory system in which a plurality of memory modules are arranged in parallel, module data wirings of each individual memory modules are connected in serial form, and each individual module data wirings do not constitute branch wirings with respect to a data bus on a motherboard of the memory system. In the memory modules, parallel access for the number of bits corresponding to the width of the memory access data bus is assured.

摘要翻译： 模块基板具有与多个存储器芯片中的各个芯片数据端子相关联地分别设置的多个模块数据端子对以及分别连接在多个模块数据端子对之间的多个模块数据布线。 多个模块数据布线连接到它们对应的芯片数据终端，并被配置为可用作存储器访问数据总线。 在并行布置多个存储器模块的存储器系统中，各个存储器模块的模块数据布线以串行形式连接，并且每个单独的模块数据布线不构成相对于主板上的数据总线的分支布线 的内存系统。 在存储器模块中，确保与存储器访问数据总线的宽度相对应的位数的并行访问。