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    Semiconductor memory device and method of manufacturing the same
    1.
    发明授权
    Semiconductor memory device and method of manufacturing the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US06778424B2

    公开(公告)日：2004-08-17

    申请号：US09986777

    申请日：2001-11-09

    申请人： Yoshihisa Iwata ,  Takashi Ohsawa ,  Takashi Yamada

    发明人： Yoshihisa Iwata ,  Takashi Ohsawa ,  Takashi Yamada

    IPC分类号： G11C1124

    CPC分类号： H01L29/7841 ,  G11C11/404 ,  G11C11/4085 ,  G11C11/4087 ,  G11C2211/4016 ,  H01L23/544 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor memory device having MIS transistors to constitute memory cells (MC), each of the MIS transistors including a semiconductor layer (12), a source region (15) formed in the semiconductor layer, a drain region (14) formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state, a main gate (13) provided between the source region and the drain region to form a channel in the channel body; and an auxiliary gate (20) provided separately from the main gate to control a potential of the channel body by capacitive coupling, the auxiliary gate being driven in synchronization with the main gate. The MIS transistor has a first data state in which the channel body is set at a first potential and a second data state in which the channel body is set at a second potential.

    摘要翻译： 一种具有构成存储单元（MC）的MIS晶体管的半导体存储器件，每个所述MIS晶体管包括半导体层（12），形成在所述半导体层中的源极区（15），形成在所述半导体层 源极区域，位于源极区域和用作浮动状态的沟道体的漏极区域之间的半导体层，设置在源极区域和漏极区域之间的主栅极（13），以在沟道中形成沟道 身体; 以及与主门分开设置的辅助门（20），以通过电容耦合来控制通道体的电位，辅助门与主门同步地驱动。 MIS晶体管具有第一数据状态，其中通道主体被设置在第一电位和第二数据状态，其中通道主体被设置在第二电位。

    Semiconductor memory device for dynamically storing data with channel body of transistor used as storage node
    3.
    发明授权
    Semiconductor memory device for dynamically storing data with channel body of transistor used as storage node 失效
    半导体存储器件，用于动态存储与用作存储节点的晶体管通道体的数据

    公开(公告)号：US07075820B2

    公开(公告)日：2006-07-11

    申请号：US10845403

    申请日：2004-05-14

    申请人： Takashi Yamada ,  Fumio Horiguchi ,  Takashi Ohsawa ,  Yoshihisa Iwata ,  Yoshiaki Asao

    发明人： Takashi Yamada ,  Fumio Horiguchi ,  Takashi Ohsawa ,  Yoshihisa Iwata ,  Yoshiaki Asao

    IPC分类号： G11C11/34 ,  G11C7/00

    CPC分类号： H01L27/108 ,  H01L21/84 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/1203 ,  H01L29/7841 ,  H01L29/785

    摘要： A semiconductor memory device includes a plurality of MIS transistors arranged at intersections of first word lines and bit lines formed on an SOI substrate and each configuring a memory cell. Each of the plurality of MIS transistors includes a channel body formed in a semiconductor layer on an insulating film and set in an electrically floating state, a first extension region formed in contact with the channel body in the semiconductor layer and arranged in a first word line direction, a gate insulating film formed on the channel body, a gate electrode formed on the gate insulating film and electrically connected to a corresponding one of the first word lines, and source and drain regions separately formed in a bit line direction in the semiconductor layer to sandwich the channel body.

    摘要翻译： 半导体存储器件包括多个MIS晶体管，其布置在形成在SOI衬底上的第一字线和位线的交点处，并且每个配置存储器单元。 多个MIS晶体管中的每一个包括形成在绝缘膜上的半导体层中并设置为电浮置状态的沟道体，与半导体层中的沟道体接触形成并布置在第一字线中的第一延伸区域 形成在沟道体上的栅极绝缘膜，形成在栅极绝缘膜上并电连接到第一字线中的相应一个的栅极电极以及在半导体层中分别形成在位线方向上的源极和漏极区域 夹住通道体。

    Nonvolatile semiconductor memory device and method for erasing data thereof
    5.
    发明授权
    Nonvolatile semiconductor memory device and method for erasing data thereof 有权
    非易失性半导体存储器件及其数据的擦除方法

    公开(公告)号：US08817538B2

    公开(公告)日：2014-08-26

    申请号：US13493370

    申请日：2012-06-11

    申请人： Kiyotaro Itagaki ,  Kunihiro Yamada ,  Yoshihisa Iwata

    发明人： Kiyotaro Itagaki ,  Kunihiro Yamada ,  Yoshihisa Iwata

    IPC分类号： G11C11/34

    CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C2213/71 ,  H01L27/11582 ,  H01L29/7926

    摘要： A control circuit is configured to set a drain-side select transistor and a source-side select transistor connected to a selected memory string to non-conductive states. The control circuit is configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in the selected memory string. The control circuit is configured to apply a second voltage to a selected word line connected to a gate of a selected memory cell in the selected memory string. The second voltage is smaller than the first voltage in an erasing operation.

    摘要翻译： 控制电路被配置为将连接到所选择的存储器串的漏极侧选择晶体管和源极侧选择晶体管设置为非导通状态。 控制电路被配置为对连接到所选择的存储器串中未选择的存储器单元的栅极的未选择字线施加第一电压。 控制电路被配置为对连接到所选择的存储器串中所选择的存储器单元的栅极的选定字线施加第二电压。 在擦除操作中第二电压小于第一电压。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    8.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号：US20110096590A1

    公开(公告)日：2011-04-28

    申请号：US12746866

    申请日：2008-09-09

    申请人： Yoshihisa Iwata

    发明人： Yoshihisa Iwata

    IPC分类号： G11C11/00

    CPC分类号： G11C11/5614 ,  G11C13/0009 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2213/71 ,  G11C2213/72

    摘要： A nonvolatile semiconductor memory device comprises a cell array having plural memory cells arranged in matrix, each memory cell including a variable resistor having a resistance reversibly variable to store data corresponding to the resistance of the variable resistor; a selection circuit operative to select a memory cell from the cell array; and a write circuit operative to execute certain voltage or current supply to the memory cell selected by the selection circuit to vary the resistance of a variable resistor in the selected memory cell to erase or write data. The write circuit terminates the voltage or current supply to the selected memory cell in accordance with resistance variation situation of the variable resistor in the selected memory cell when current flowing in the selected memory cell reaches a certain level appeared after the data erase or write.

    摘要翻译： 非易失性半导体存储器件包括具有以矩阵形式排列的多个存储单元的单元阵列，每个存储单元包括具有可逆可变电阻的可变电阻器，用于存储对应于可变电阻器的电阻的数据; 选择电路，用于从所述单元阵列中选择存储单元; 以及写入电路，用于对由选择电路选择的存储器单元执行一定的电压或电流供应，以改变所选择的存储器单元中的可变电阻器的电阻以擦除或写入数据。 当电流在所选存储单元中流动的电流达到数据擦除或写入之后出现的一定水平时，写入电路根据所选存储单元中的可变电阻器的电阻变化情况，终止对所选存储单元的电压或电流供应。

    SENSE AMPLIFIER
    9.
    发明申请
    SENSE AMPLIFIER 有权
    感应放大器

    公开(公告)号：US20100067283A1

    公开(公告)日：2010-03-18

    申请号：US12624103

    申请日：2009-11-23

    申请人： Yoshihiro UEDA ,  Yoshihisa Iwata ,  Toshiaki Edahiro ,  Toshihiro Suzuki

    发明人： Yoshihiro UEDA ,  Yoshihisa Iwata ,  Toshiaki Edahiro ,  Toshihiro Suzuki

    IPC分类号： G11C7/08 ,  G11C11/00 ,  G11C11/02 ,  G11C11/16

    CPC分类号： G11C7/065 ,  G11C7/062 ,  G11C7/12 ,  G11C11/1673 ,  G11C16/0491 ,  G11C16/26 ,  G11C17/126 ,  G11C2207/002 ,  G11C2207/063

    摘要： A sense amplifier according to an example of the present invention has first, second, third and fourth FETs with a flip-flop connection. A drain of a fifth FET is connected to a first input node, and its source is connected to a power source node. A drain of a sixth FET is connected to a second input node, and its source is connected to the power source node. A sense operation is started by charging a first output node from the first input node with a first current and by charging a second output node from the second input node with a second current. The fifth and sixth FET are turned on after starting the sense operation.

    摘要翻译： 根据本发明的示例的读出放大器具有触发器连接的第一，第二，第三和第四FET。 第五FET的漏极连接到第一输入节点，并且其源极连接到电源节点。 第六FET的漏极连接到第二输入节点，其源极连接到电源节点。 通过用第一电流从第一输入节点充电第一输出节点并且通过用第二电流从第二输入节点对第二输出节点充电来启动感测操作。 开始感测操作后，第五和第六FET导通。

    MAGNETORESISTIVE EFFECT ELEMENT AND MAGNETIC MEMORY
    10.
    发明申请
    MAGNETORESISTIVE EFFECT ELEMENT AND MAGNETIC MEMORY 有权
    磁电效应元件和磁记忆

    公开(公告)号：US20080130176A1

    公开(公告)日：2008-06-05

    申请号：US12019657

    申请日：2008-01-25

    申请人： Tadashi KAI ,  Masahiko Nakayama ,  Sumio Ikegawa ,  Yoshiaki Fukuzumi ,  Yoshihisa Iwata

    发明人： Tadashi KAI ,  Masahiko Nakayama ,  Sumio Ikegawa ,  Yoshiaki Fukuzumi ,  Yoshihisa Iwata

    IPC分类号： G11B5/33

    CPC分类号： H01L43/08 ,  G11C11/16 ,  H01L27/222

    摘要： A magnetoresistive effect element includes a nonmagnetic layer having mutually facing first and second surfaces. A reference layer is provided on the first surface and has a fixed magnetization direction. A magnetization variable layer is provided on the second surface, has variable magnetization direction, and has a planer shape including a rectangular part, a first projected part, and a second projected part. The rectangular part has mutually facing first and second longer sides and mutually facing first and second shorter sides. The first projected part projects from the first longer side at a position shifted from the center toward the first shorter side. The second projected part projects from the second longer side at a position shifted from the center toward the second shorter side.

    摘要翻译： 磁阻效应元件包括具有相互面对的第一和第二表面的非磁性层。 参考层设置在第一表面上并具有固定的磁化方向。 磁化变化层设置在第二表面上，具有可变的磁化方向，并且具有包括矩形部分，第一突出部分和第二突出部分的平面形状。 矩形部分具有相互面对的第一和第二长边以及相互面对的第一和第二短边。 第一突出部从第一长边突出的位置从中心向第一短边移动。 第二突出部从第二长边突出的位置从中心向第二短边移动。