公开(公告)号：US5827436A

公开(公告)日：1998-10-27

申请号：US616964

申请日：1996-03-15

申请人： Yukihiro Kamide ,  Yuji Takaoka ,  Yasuaki Yamamichi

发明人： Yukihiro Kamide ,  Yuji Takaoka ,  Yasuaki Yamamichi

IPC分类号： C23F4/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  C23F1/20 ,  H01L21/00

CPC分类号： H01L21/32136 ,  C23F4/00

摘要： A mixed etching gas consisting of boron trichloride, a rare gas, and chlorine is used for etching of an aluminum metal film by dry-etching. In the first step, high frequency power is used to etch and remove alloy grains which tend to form residues and to etch an aluminum metal film in an anisotropic mode. Just before the under-layered silicon film is exposed, the frequency power is lowered but is kept higher than the minimum power required for anisotropic etching to enable etching selectivity with respect to the silicon dioxide film to be achieved.

摘要翻译： 由三氯化硼，稀有气体和氯组成的混合蚀刻气体用于通过干蚀刻蚀刻铝金属膜。 在第一步中，使用高频功率来蚀刻和去除倾向于形成残余物的合金晶粒，并以各向异性模式蚀刻铝金属膜。 在曝光下层硅膜之前，频率功率降低，但是保持高于各向异性蚀刻所需的最小功率以实现相对于二氧化硅膜的蚀刻选择性。

公开(公告)号：US07135378B2

公开(公告)日：2006-11-14

申请号：US10719926

申请日：2003-11-21

申请人： Yuji Takaoka ,  Yukihiro Kamide ,  Teruo Hirayama ,  Masaki Hatano

发明人： Yuji Takaoka ,  Yukihiro Kamide ,  Teruo Hirayama ,  Masaki Hatano

IPC分类号： H01L21/76 ,  H01L21/46 ,  H01L23/544

CPC分类号： H01L24/82 ,  H01L21/568 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/3512 ,  H01L2924/00

摘要： A semiconductor device of MCM type allowing high-density assembly and a process of fabricating the same is provided. There are provided semiconductor chips mounted on a supporting substrate and incrusted in an insulation film on the supporting substrate and wiring formed in the insulation film so as to connect to each semiconductor chip through connection holes provided in the insulation film. Then, an interlayer dielectric covers such wiring that is connected to an upper layer wiring, through connection holes provided in such interlayer dielectric. In addition, an upper layer insulation film covers the upper layer wiring, and an electrode, connected to such upper layer wiring through another connection hole, is provided on such upper layer insulation film.

摘要翻译： 提供允许高密度组装的MCM型半导体器件及其制造方法。 提供安装在支撑基板上的半导体芯片，并且被覆在支撑基板上的绝缘膜和形成在绝缘膜中的布线，以便通过设置在绝缘膜中的连接孔连接到每个半导体芯片。 然后，通过设置在该层间电介质中的连接孔，层间电介质覆盖与上层布线连接的布线。 此外，上层绝缘膜覆盖上层布线，并且在这种上层绝缘膜上设置有通过另一连接孔连接到这种上层布线的电极。

公开(公告)号：US08564101B2

公开(公告)日：2013-10-22

申请号：US12348988

申请日：2009-01-06

申请人： Yoshimichi Harada ,  Masami Suzuki ,  Yoshihiro Nabe ,  Yuji Takaoka ,  Tatsuo Suemasu ,  Hideyuki Wada ,  Masanobu Saruta

发明人： Yoshimichi Harada ,  Masami Suzuki ,  Yoshihiro Nabe ,  Yuji Takaoka ,  Tatsuo Suemasu ,  Hideyuki Wada ,  Masanobu Saruta

IPC分类号： H01L29/40

CPC分类号： H01L27/14618 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/16 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2224/05599

摘要： A semiconductor apparatus having a through-hole interconnection in a semiconductor substrate. An insulating layer is formed on the semiconductor substrate. A via hole is formed through the semiconductor substrate and the insulating layer. The through-hole interconnection has another insulating layer formed in the via hole and a conductive layer formed thereon. The insulating layer formed in the via hole is formed such as to substantially planarize an inner surface of the via hole.

摘要翻译： 一种在半导体衬底中具有通孔互连的半导体器件。 绝缘层形成在半导体衬底上。 通过半导体衬底和绝缘层形成通孔。 通孔布线具有形成在通孔中的另一绝缘层和形成在其上的导电层。 形成在通孔中的绝缘层形成为使得通孔的内表面基本上平坦化。

公开(公告)号：US06936525B2

公开(公告)日：2005-08-30

申请号：US10236771

申请日：2002-09-06

申请人： Kazuo Nishiyama ,  Hiroshi Ozaki ,  Yuji Takaoka ,  Teruo Hirayama

发明人： Kazuo Nishiyama ,  Hiroshi Ozaki ,  Yuji Takaoka ,  Teruo Hirayama

IPC分类号： H01L21/683 ,  H01L21/301 ,  H01L21/48 ,  H01L21/56 ,  H01L21/60 ,  H01L21/68 ,  H01L23/12 ,  H01L23/31 ,  H01L23/485 ,  H01L21/46 ,  H01L21/78

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02166 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05571 ,  H01L2224/1131 ,  H01L2224/12105 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2224/73203 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacturing the semiconductor chips comprises the steps of: pasting on a substrate an adhesive sheet having a property to retain its adhesive strength prior to a processing, then lose its adhesive strength after the processing; fixing a plurality of non-defective bare chips on this adhesive sheet, with their Al electrode pad surfaces facing down; coating a resin on a whole area other than the Al electrode pad surfaces of the plurality of non-defective bare chips including interspaces therebetween; applying a predetermined process to the adhesive sheet to weaken its adhesive strength of the adhesive sheet; peeling off a pseudo wafer bonding non-defective bare chips; and dicing the plurality of non-defective bare chips into a discrete non-defective electronic part by cutting the pseudo wafer at a position of the resin between respective non-defective bare chips.

摘要翻译： 制造半导体芯片的方法包括以下步骤：在基板上粘贴具有在加工之前保持其粘合强度的性能的粘合片，然后在加工后失去其粘合强度; 在该粘合片上固定多个无缺陷裸芯片，其Al电极焊盘表面朝下; 在除了包括它们之间的间隙的多个无缺陷裸芯片的Al电极焊盘表面以外的整个区域上涂覆树脂; 对粘合片施加预定的处理以削弱其粘合片的粘合强度; 剥离伪晶片结合无缺陷裸芯片; 并且通过在各个无缺陷裸芯片之间的树脂的位置处切割伪晶片将多个无缺陷裸芯片切割成离散的无缺陷电子部件。

公开(公告)号：US07402901B2

公开(公告)日：2008-07-22

申请号：US11366123

申请日：2006-03-02

申请人： Masaki Hatano ,  Yuji Takaoka

发明人： Masaki Hatano ,  Yuji Takaoka

IPC分类号： H01L23/06

CPC分类号： H01L25/0655 ,  H01L23/5389 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/10253 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/00 ,  H01L2924/00014

摘要： The present invention provides a semiconductor device that is inexpensive and can suppress signal transmission delay, and a manufacturing method thereof. The semiconductor device includes: a plurality of semiconductor chips; a semiconductor substrate that has, on the same surface thereof, a chip-to-chip interconnection for electrically connecting the plurality of semiconductor chips to each other, and a plurality of chip-connection pads connected to the chip-to-chip interconnection; and a wiring board that has a plurality of lands of which pitch is larger than a pitch of the chip-connection pads, wherein a major surface of each of the plurality of semiconductor chips is connected to the chip-connection pads via a first connector so that the plurality of semiconductor chips are mounted on the semiconductor substrate, and an external-connection pad is formed on the major surface other than a region facing the semiconductor substrate, and is connected to the land on the wiring board via a second connector.

摘要翻译： 本发明提供一种廉价且可以抑制信号传输延迟的半导体器件及其制造方法。 半导体器件包括：多个半导体芯片; 半导体衬底，其同一表面上具有用于将多个半导体芯片彼此电连接的芯片至芯片互连以及连接到芯片至芯片互连的多个芯片连接焊盘; 以及布线板，其具有多个间距大于芯片连接焊盘的间距的焊盘，其中，多个半导体芯片中的每一个的主表面经由第一连接器连接到芯片连接焊盘， 多个半导体芯片安装在半导体基板上，并且外部连接焊盘形成在除了面向半导体基板的区域之外的主表面上，并且经由第二连接器连接到布线板上的焊盘。

公开(公告)号：US20120286387A1

公开(公告)日：2012-11-15

申请号：US13553389

申请日：2012-07-19

申请人： Yoshihiro Nabe ,  Hiroshi Asami ,  Yuji Takaoka ,  Yoshimichi Harada

发明人： Yoshihiro Nabe ,  Hiroshi Asami ,  Yuji Takaoka ,  Yoshimichi Harada

IPC分类号： H01L31/0224

CPC分类号： H01L27/14618 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L27/14634 ,  H01L27/14636 ,  H01L31/0224 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/1134 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16238 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.

摘要翻译： 一种半导体器件，包括具有相对面对的第一表面和第二表面的半导体衬底，所述第一表面是活性表面，并且在其上设置有电子元件，焊接电极，用于在所述电子元件的周边部分中连接到所述电子元件， 活性表面，从第二表面朝向焊盘电极延伸以便不到达半导体衬底的第一表面的第一开口，形成为从第一开口的底表面到达焊盘电极并具有较小直径的第二开口 形成为覆盖第一开口和第二开口的侧壁表面的绝缘层和在绝缘层内部形成的导电层，以覆盖至少绝缘层的内壁表面和 第二开口的底面。

公开(公告)号：US20110136342A1

公开(公告)日：2011-06-09

申请号：US13027614

申请日：2011-02-15

申请人： Yoshimichi Harada ,  Masami Suzuki ,  Yoshihiro Nabe ,  Yuji Takaoka ,  Tatsuo Suemasu ,  Hideyuki Wada ,  Masanobu Saruta

发明人： Yoshimichi Harada ,  Masami Suzuki ,  Yoshihiro Nabe ,  Yuji Takaoka ,  Tatsuo Suemasu ,  Hideyuki Wada ,  Masanobu Saruta

IPC分类号： H01L21/768

CPC分类号： H01L27/14618 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/16 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2224/05599

摘要： A semiconductor apparatus including a semiconductor substrate, an insulating layer, a via hole, and a through-hole interconnection is provided. The insulating layer is formed on the semiconductor substrate. The via hole is formed through the semiconductor substrate and the insulating layer. The through-hole interconnection has a conductive layer formed on an insulating layer in the via hole. The surface of the insulating layer formed on the inner surface of the via hole is substantially planarized by filling a recessed portion on a boundary between the semiconductor substrate and the insulating layer formed on the semiconductor substrate.

摘要翻译： 提供了包括半导体衬底，绝缘层，通孔和通孔互连的半导体器件。 绝缘层形成在半导体衬底上。 通孔形成为穿过半导体衬底和绝缘层。 通孔互连具有形成在通孔中的绝缘层上的导电层。 通过在半导体衬底和形成在半导体衬底上的绝缘层之间的边界填充凹陷部分，在通孔的内表面上形成的绝缘层的表面基本平坦化。

公开(公告)号：US20090200679A1

公开(公告)日：2009-08-13

申请号：US12348988

申请日：2009-01-06

申请人： Yoshimichi Harada ,  Masami Suzuki ,  Yoshihiro Nabe ,  Yuji Takaoka ,  Tatsuo Suemasu ,  Hideyuki Wada ,  Masanobu Saruta

发明人： Yoshimichi Harada ,  Masami Suzuki ,  Yoshihiro Nabe ,  Yuji Takaoka ,  Tatsuo Suemasu ,  Hideyuki Wada ,  Masanobu Saruta

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L27/14618 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/16 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2224/05599

摘要： A semiconductor apparatus including a semiconductor substrate, an insulating layer, a via hole, and a through-hole interconnection is provided. The insulating layer is formed on the semiconductor substrate. The via hole is formed through the semiconductor substrate and the insulating layer. The through-hole interconnection has a conductive layer formed on an insulating layer in the via hole. The surface of the insulating layer formed on the inner surface of the via hole is substantially planarized by filling a recessed portion on a boundary between the semiconductor substrate and the insulating layer formed on the semiconductor substrate.

摘要翻译： 提供了包括半导体衬底，绝缘层，通孔和通孔互连的半导体器件。 绝缘层形成在半导体衬底上。 通孔形成为穿过半导体衬底和绝缘层。 通孔互连具有形成在通孔中的绝缘层上的导电层。 通过在半导体衬底和形成在半导体衬底上的绝缘层之间的边界填充凹陷部分，在通孔的内表面上形成的绝缘层的表面基本平坦化。

公开(公告)号：US20080138932A1

公开(公告)日：2008-06-12

申请号：US11971271

申请日：2008-01-09

申请人： Masaki Hatano ,  Yuji Takaoka

发明人： Masaki Hatano ,  Yuji Takaoka

IPC分类号： H01L21/60

CPC分类号： H01L25/0655 ,  H01L23/5389 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/10253 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/00 ,  H01L2924/00014

摘要： The present invention provides a semiconductor device that is inexpensive and can suppress signal transmission delay, and a manufacturing method thereof. The semiconductor device includes: a plurality of semiconductor chips; a semiconductor substrate that has, on the same surface thereof, a chip-to-chip interconnection for electrically connecting the plurality of semiconductor chips to each other, and a plurality of chip-connection pads connected to the chip-to-chip interconnection; and a wiring board that has a plurality of lands of which pitch is larger than a pitch of the chip-connection pads, wherein a major surface of each of the plurality of semiconductor chips is connected to the chip-connection pads via a first connector so that the plurality of semiconductor chips are mounted on the semiconductor substrate, and an external-connection pad is formed on the major surface other than a region facing the semiconductor substrate, and is connected to the land on the wiring board via a second connector.

摘要翻译： 本发明提供一种廉价且可以抑制信号传输延迟的半导体器件及其制造方法。 半导体器件包括：多个半导体芯片; 半导体衬底，其同一表面上具有用于将多个半导体芯片彼此电连接的芯片至芯片互连以及连接到芯片至芯片互连的多个芯片连接焊盘; 以及布线板，其具有多个间距大于芯片连接焊盘的间距的焊盘，其中，多个半导体芯片中的每一个的主表面经由第一连接器连接到芯片连接焊盘， 多个半导体芯片安装在半导体基板上，并且外部连接焊盘形成在除了面向半导体基板的区域之外的主表面上，并且经由第二连接器连接到布线板上的焊盘。

公开(公告)号：US08273657B2

公开(公告)日：2012-09-25

申请号：US13027614

申请日：2011-02-15

申请人： Yoshimichi Harada ,  Masami Suzuki ,  Yoshihiro Nabe ,  Yuji Takaoka ,  Tatsuo Suemasu ,  Hideyuki Wada ,  Masanobu Saruta

发明人： Yoshimichi Harada ,  Masami Suzuki ,  Yoshihiro Nabe ,  Yuji Takaoka ,  Tatsuo Suemasu ,  Hideyuki Wada ,  Masanobu Saruta

IPC分类号： H01L21/44

CPC分类号： H01L27/14618 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/16 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2224/05599

摘要： A method for manufacturing a semiconductor apparatus having a through-hole interconnection in a semiconductor substrate. An insulating layer is formed on the semiconductor substrate. A via hole is formed through the semiconductor substrate and the insulating layer. Another insulating layer is formed in the via hole, and a conductive layer of the through-hole interconnection is subsequently formed. The insulating layer formed in the via hole is formed such as to substantially planarize an inner surface of the via hole.

摘要翻译： 一种在半导体衬底中具有通孔互连的半导体装置的制造方法。 绝缘层形成在半导体衬底上。 通过半导体衬底和绝缘层形成通孔。 在通孔中形成另一绝缘层，随后形成通孔互连的导电层。 形成在通孔中的绝缘层形成为使得通孔的内表面基本上平坦化。