公开(公告)号：US5286926A

公开(公告)日：1994-02-15

申请号：US868568

申请日：1992-04-15

申请人： Yukihiro Kimura ,  Nobuhiko Miyawaki ,  Masao Kuroda

发明人： Yukihiro Kimura ,  Nobuhiko Miyawaki ,  Masao Kuroda

IPC分类号： H01L23/12 ,  H01L23/14 ,  H01L23/498 ,  H05K1/00

CPC分类号： H01L23/49827 ,  H01L2223/6622 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025

摘要： The present integrated circuit package provides both a high density of conductor poles, and reduced crosstalk noise between the conductor poles. The conductor poles are arranged within a selected number of holes in an insulating substrate. Metallized layers for shielding the conductor poles are provided on the walls of the holes in the insulating substrate which receive the conductor poles. In addition, an insulating layer is provided on the inner circumferences of the metallized layers, which insulating layers directly surround the conductor poles to preclude direct contact between the conductor poles and the metallized layers.

摘要翻译： 本集成电路封装提供高密度的导体极，并减少导体极之间的串扰噪声。 导体极被布置在绝缘基板中的选定数量的孔内。 用于屏蔽导体极的金属化层设置在接收导体极的绝缘基板中的孔的壁上。 此外，绝缘层设置在金属化层的内周上，这些绝缘层直接围绕导体极，以防止导体极与金属化层之间的直接接触。

公开(公告)号：US5293502A

公开(公告)日：1994-03-08

申请号：US868567

申请日：1992-04-15

申请人： Yukihiro Kimura ,  Nobuhiko Miyawaki ,  Masao Kuroda

发明人： Yukihiro Kimura ,  Nobuhiko Miyawaki ,  Masao Kuroda

IPC分类号： H01L23/13 ,  H01L21/48 ,  H01L23/12 ,  H01L23/14 ,  H01L23/498 ,  H05K01/00

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025

摘要： The present integrated circuit package provides both a high density of conductor poles, and reduced crosstalk noises between the conductor poles. The conductor poles are received within holes in an insulating substrate. The insulating substrate has a laminated, multi-layer ceramic substrate structure comprising insulating plates having metallized layers thereon which constitute a portion of the walls of the holes. In addition, insulating layers for insulating the metallized layers from the conductor poles are formed within a selected number of the holes.

摘要翻译： 本集成电路封装既提供高导体极的高密度，又减少导体极之间的串扰噪声。 导体极接收在绝缘基板的孔内。 绝缘基板具有层叠的多层陶瓷基板结构，其包括在其上形成有金属化层的绝缘板，其构成孔的壁的一部分。 此外，在选定数量的孔内形成用于使金属化层与导体极绝缘的绝缘层。

公开(公告)号：US5093186A

公开(公告)日：1992-03-03

申请号：US584641

申请日：1990-09-19

申请人： Yukihiro Kimura ,  Nobuhiko Miyawaki ,  Sumihito Tominaga ,  Rokuro Kanbe

发明人： Yukihiro Kimura ,  Nobuhiko Miyawaki ,  Sumihito Tominaga ,  Rokuro Kanbe

IPC分类号： H05K3/46 ,  H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H05K3/40

CPC分类号： H05K1/0271 ,  H05K3/4061 ,  H05K1/0306 ,  H05K1/092 ,  H05K2201/0269 ,  H05K2201/068 ,  H05K3/4611 ,  H05K3/4629 ,  Y10S428/901 ,  Y10T428/24917

摘要： A multilayer ceramic wiring board including a ceramic board having a plurality of through-holes and formed by laminating three or more green sheets of a ceramic material and burning a laminate of the green sheets, and a plurality of conductors provided in the through-holes. Each of the conductors is formed of a ceramic material and a conductive material in combination. The ceramic board is composed of a pair of upper and lower layer portions each having at least an outermost surface layer and an inner layer portion disposed between the upper and lower portions. The conductors are composed of an outer conductor portion formed in the upper and lower layer portions and an inner conductor portion formed in the inner layer portion. The outer conductor portion has a content ratio of the ceramic material higher than that of the inner conductor portion. Accordingly, the generation of cracks in the outer conductor portion disposed at the upper and lower layer portions of the ceramic board can be prevented, and an electric resistance can be reduced.

摘要翻译： 一种多层陶瓷布线板，包括具有多个通孔的陶瓷板，并且通过层叠三种或更多种陶瓷材料的生片并烧制生片的层压体，以及设置在通孔中的多个导体。 每个导体由陶瓷材料和导电材料组合形成。 陶瓷板由一对上下层部分组成，每一层至少具有最外表面层和设置在上部和下部之间的内层部分。 导体由形成在上层部和下层部中的外部导体部和形成在内层部的内部导体部构成。 外导体部分的陶瓷材料的含量比高于内导体部分的含量比。 因此，可以防止在布置在陶瓷板的上层和下层部分的外导体部分中产生裂纹，并且可以降低电阻。

公开(公告)号：US20070226715A1

公开(公告)日：2007-09-27

申请号：US11477165

申请日：2006-06-28

申请人： Yukihiro Kimura ,  Masakazu Hayashi ,  Masafumi Hashiguchi ,  Hidetoshi Hattori

发明人： Yukihiro Kimura ,  Masakazu Hayashi ,  Masafumi Hashiguchi ,  Hidetoshi Hattori

IPC分类号： G06F9/45

CPC分类号： G06F9/45516

摘要： A recovery virtual machine acquires execution frequency information from a file, and converts a procedure, of which execution frequency is high in the execution frequency information acquired, to native code, and the time for starting the conversion is thereby reduced. Furthermore, by performing conversion at a timing at which a target procedure is invoked, load occurring due to the conversion is distributed, to prevent occurrence of failure in execution of an application caused by the load occurring due to the conversion.

摘要翻译： 恢复虚拟机从文件获取执行频率信息，并且将所获取的执行频率信息中的执行频率高的过程转换为本地代码，从而减少开始转换的时间。 此外，通过在调用目标过程的定时进行转换，分配由于转换而发生的负载，以防止由于转换而产生的负载导致的应用执行失败。

公开(公告)号：US5400210A

公开(公告)日：1995-03-21

申请号：US80107

申请日：1993-06-23

申请人： Noriyasu Sugimoto ,  Yukihiro Kimura ,  Masaharu Seto

发明人： Noriyasu Sugimoto ,  Yukihiro Kimura ,  Masaharu Seto

IPC分类号： H01B3/12 ,  H01G4/08 ,  H01G4/12 ,  H01L23/12 ,  H01L23/15 ,  H05K1/16 ,  H05K3/46 ,  H01G4/10

CPC分类号： H01G4/08

摘要： In a substrate having built-in capacitor which is incorporated in and united with an insulator, the capacitor has a dielectric layer made of a silicon nitride-based ceramic containing silicon carbide in an amount of from 13 to 30% by weight.

摘要翻译： 在具有内置电容器的衬底中，该绝缘体并入并结合在一起，该电容器具有由含有13至30重量％的碳化硅的氮化硅基陶瓷制成的电介质层。

公开(公告)号：US5250244A

公开(公告)日：1993-10-05

申请号：US911782

申请日：1992-07-10

申请人： Yukihiro Kimura ,  Sumihito Tominaga ,  Rokuro Kanbe

发明人： Yukihiro Kimura ,  Sumihito Tominaga ,  Rokuro Kanbe

IPC分类号： C04B35/111 ,  C04B35/185 ,  C04B35/622 ,  C04B35/64

CPC分类号： C04B35/622 ,  C04B35/111 ,  C04B35/185

摘要： A method of producing a sintered body by molding a mixture of a ceramic base powder, a sintering assistant powder and an organic binder and sintering the molded body in a non-oxidizing atmosphere is disclosed in which the ceramic base powder has such a particle size distribution that the amount of powder particles not greater than 1.0 .mu.m in size is not more than 15% by weight and the average particle diameter is not greater than 5 .mu.m. According to the method, therefore, sufficient passage of gas is secured in a degreasing step, resulting in an enhanced degreasing efficiency and exellent sintering properties. Where the sintering assistant powder has such a particle size distribution that the amount of powder particles not greater than 10 .mu.m in size is not more than 5% by weight, the amount of coarse powder is extremely small and, therefore, large voids are not formed. It is thus possible to produce easily a high-quality sintered body by controlling the respective particle size distributions of the powders.

摘要翻译： 公开了一种通过模制陶瓷基底粉末，烧结辅助粉末和有机粘合剂的混合物并在非氧化性气氛中烧结成型体来制造烧结体的方法，其中陶瓷基础粉末具有这样的粒度分布 不大于1.0μm的粉末颗粒的量不大于15重量％，平均粒径不大于5μm。 因此，根据该方法，在脱脂工序中确保充分的气体通过，从而提高脱脂效率和良好的烧结性能。 当烧结辅助粉末具有这样的粒度分布，其尺寸不大于10微米的粉末颗粒的量不大于5重量％时，粗粉末的量非常小，因此，大的空隙不是 形成。 因此，通过控制粉末的各自的粒度分布，可以容易地制造高品质的烧结体。

公开(公告)号：US4690872A

公开(公告)日：1987-09-01

申请号：US876643

申请日：1986-06-16

申请人： Norio Kato ,  Shunkichi Nozaki ,  Yukihiro Kimura ,  Rokuro Kambe

发明人： Norio Kato ,  Shunkichi Nozaki ,  Yukihiro Kimura ,  Rokuro Kambe

IPC分类号： H05B3/20 ,  C04B41/50 ,  C04B41/87 ,  C21B9/00 ,  C23C16/42 ,  H05B3/06 ,  H05B3/22

CPC分类号： C04B41/009 ,  C04B41/5062 ,  C04B41/87 ,  C21B9/00 ,  C23C16/42 ,  H05B3/06

摘要： A ceramic heater comprising a ceramic substrate is described which has formed thereon a layer of a silicide of an element selected from groups IVa, Va and VIa of the periodic table. The heater has stable temperature vs. resistance characteristics, has high mechanical strength and produces the desired temperature in a very short period of time.

摘要翻译： 描述了一种陶瓷加热器，其包括陶瓷基板，其上形成了选自元素周期表的IVa，Va和VIa族元素的硅化物层。 加热器具有稳定的温度对电阻特性，具有高的机械强度并在很短的时间内产生所需的温度。

公开(公告)号：US08332845B2

公开(公告)日：2012-12-11

申请号：US11477165

申请日：2006-06-28

申请人： Yukihiro Kimura ,  Masakazu Hayashi ,  Masafumi Hashiguchi ,  Hidetoshi Hattori

发明人： Yukihiro Kimura ,  Masakazu Hayashi ,  Masafumi Hashiguchi ,  Hidetoshi Hattori

IPC分类号： G06F9/455

CPC分类号： G06F9/45516

摘要： A recovery virtual machine acquires execution frequency information from a file, and converts a procedure, of which execution frequency is high in the execution frequency information acquired, to native code, and the time for starting the conversion is thereby reduced. Furthermore, by performing conversion at a timing at which a target procedure is invoked, load occurring due to the conversion is distributed, to prevent occurrence of failure in execution of an application caused by the load occurring due to the conversion.

摘要翻译： 恢复虚拟机从文件获取执行频率信息，并且将所获取的执行频率信息中的执行频率高的过程转换为本地代码，从而减少开始转换的时间。 此外，通过在调用目标过程的定时进行转换，分配由于转换而发生的负载，以防止由于转换而产生的负载导致的应用执行失败。

公开(公告)号：US07102085B2

公开(公告)日：2006-09-05

申请号：US10103039

申请日：2002-03-22

申请人： Sumio Ohta ,  Mitsuru Tamaki ,  Yukihiro Kimura

发明人： Sumio Ohta ,  Mitsuru Tamaki ,  Yukihiro Kimura

IPC分类号： H05K1/16

CPC分类号： H05K1/0231 ,  H01L23/49833 ,  H01L23/642 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/30107 ,  H01L2924/3511 ,  H05K1/186 ,  H05K3/4602 ,  H01L2924/00 ,  H01L2224/05599

摘要： A wiring substrate is configured such that a build-up layer is formed only on a front surface (a single side) of a core substrate and such that the distance between a semiconductor device mounted on the front surface thereof and an electronic component mounted on the back surface thereof or incorporated therein behind the back surface is reduced to thereby enhance electrical characteristics of an electrically continuous path therebetween, and whose overall strength is enhanced so as not to be prone to deflection or warpage. The wiring substrate includes a relatively thin first core substrate 2 having a front surface 3 and a back surface 4; a relatively thick second core substrate 6 superposed on the back surface 4 of the first core substrate 2 and having a through opening 9 formed therein, the first substrate 2 and the through opening 9 defining a recess 9; and a build-up layer BU formed on the front surface 3 of the first core substrate 2 and including wiring layers 16 and 25 and dielectric layers 23 and 26.

公开(公告)号：US06979890B2

公开(公告)日：2005-12-27

申请号：US11127192

申请日：2005-05-12

申请人： Rokuro Kambe ,  Tetsuya Kasiwagi ,  Yukihiro Kimura ,  Yasuhiro Sugimoto ,  Kazuhiro Suzuki

发明人： Rokuro Kambe ,  Tetsuya Kasiwagi ,  Yukihiro Kimura ,  Yasuhiro Sugimoto ,  Kazuhiro Suzuki

IPC分类号： H01F5/00 ,  H01L23/02 ,  H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H05K1/11 ,  H05K3/46

CPC分类号： H01L23/50 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/112 ,  H05K3/4602 ,  H05K3/4694 ,  H05K2201/0187 ,  H05K2201/10674 ,  H01L2224/05599

摘要： An intermediate substrate is provided which reduces the effect of the difference in the coefficients of linear expansion between the terminals of the substrate and those of a semiconductor integrated circuit device, and which thus lowers the likelihood of disconnection due to thermal stress. The intermediate substrate, which is a planar member made of a polymeric material, includes a substrate core including a main core body having formed therein a sub-core compartment, and a ceramic sub-core section accommodated in the compartment. A first terminal array on the first principal surface side includes two types of terminals, functioning either as power source terminals or ground terminals, and a signal terminal. The array occupies an area entirely included within an orthogonally projected region of the sub-core section projected onto a reference plane parallel to the planar surface of the substrate core.

摘要翻译： 提供了一种中间衬底，其减小了衬底的端子与半导体集成电路器件的端子之间的线性膨胀系数的差异的影响，从而降低了由于热应力引起的断开的可能性。 作为由聚合物材料制成的平面构件的中间基板包括：基材芯，其包括形成有副芯隔室的主芯体和容纳在隔室中的陶瓷副芯部。 第一主表面侧的第一端子阵列包括用作电源端子或接地端子的两种类型的端子和信号端子。 阵列占据完全包括在子芯部分的正交投影区域内的区域，该区域投影到平行于衬底芯的平面表面的参考平面上。