公开(公告)号：US4896199A

公开(公告)日：1990-01-23

申请号：US169001

申请日：1988-03-16

申请人： Yukio Tsuzuki ,  Masami Yamaoka

发明人： Yukio Tsuzuki ,  Masami Yamaoka

IPC分类号： H01L23/58 ,  H01L21/822 ,  H01L23/34 ,  H01L27/02 ,  H01L27/04 ,  H01L29/78

CPC分类号： H01L29/7803 ,  H01L23/34 ,  H01L27/0248 ,  H01L29/7804 ,  H01L29/7808 ,  H01L2924/0002

摘要： A semiconductor substrate has a power region and a control region. The control region is located in the center portion of the substrate, and the power region surrounds the control region and is separated therefrom. A vertical type, MOS transistor, i.e., an active semiconductor element, is formed on the power region. An insulation film is formed on part of the control region. A polycrystalline silicon diode, which functions as a heat-sensitive element, is formed on the insulation film. A control section comprising a lateral type, MOS transistor is also formed on the control region. The lateral type, MOS transistor is connected to receive a signal form the polycrystalline silicon diode. Further, a polycrystalline silicon resistor, which determines a circuit constant, is formed on the insulation film. The MOS transistor protects the active semiconductor element in response to a signal supplied from the heat-sensitive element showing that the temperature of the semiconductor substrate has risen above a predetermined value. For example, the active semiconductor element may be disabled until the detected temperature drops below a predetermined value.

公开(公告)号：US4760434A

公开(公告)日：1988-07-26

申请号：US935718

申请日：1986-11-28

申请人： Yukio Tsuzuki ,  Masami Yamaoka

发明人： Yukio Tsuzuki ,  Masami Yamaoka

IPC分类号： H01L23/58 ,  H01L21/822 ,  H01L23/34 ,  H01L27/02 ,  H01L27/04 ,  H01L29/78 ,  G05F1/40 ,  H01L23/56 ,  H01L31/00

CPC分类号： H01L29/7803 ,  H01L23/34 ,  H01L27/0248 ,  H01L29/7804 ,  H01L29/7808 ,  H01L2924/0002

摘要： A semiconductor substrate has a power region and a control region. The control region is located in the center portion of the substrate, and the power region surrounds the control region and is separated therefrom. A vertical type, MOS transistor, i.e., an active semiconductor element, is formed on the power region. An insulation film is formed on part of the control region. A polycrystalline silicon diode, which functions as a heat-sensitive element, is formed on the insulation film. A control section comprising a lateral type, MOS transistor is also formed on the control region. The lateral type, MOS transistor is connected to receive a signal form the polycrystalline silicon diode. Further, a polycrystalline silicon resistor, which determines a circuit constant, is formed on the insulation film. The MOS transistor protects the active semiconductor element in response to a signal supplied from the heat-sensitive element showing that the temperature of the semiconductor substrate has risen above a predetermined value. For example, the active semiconductor element may be disabled until the detected temperature drops below a predetermined value.

摘要翻译： 半导体衬底具有功率区域和控制区域。 控制区域位于基板的中心部分，功率区域围绕控制区域并与之分离。 在功率区域上形成垂直型MOS晶体管即有源半导体元件。 在控制区域的一部分上形成绝缘膜。 在绝缘膜上形成用作热敏元件的多晶硅二极管。 在控制区域上还形成有包括横向型MOS晶体管的控制部。 横向型MOS晶体管被连接以从多晶硅二极管接收信号。 此外，在绝缘膜上形成确定电路常数的多晶硅电阻器。 MOS晶体管响应于来自热敏元件的信号保护有源半导体元件，表明半导体衬底的温度已经升高到预定值以上。 例如，可以禁用活性半导体元件，直到检测到的温度下降到预定值以下。

公开(公告)号：US4680608A

公开(公告)日：1987-07-14

申请号：US697571

申请日：1985-02-01

申请人： Yukio Tsuzuki ,  Masami Yamaoka ,  Shoji Toyoshima

发明人： Yukio Tsuzuki ,  Masami Yamaoka ,  Shoji Toyoshima

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/08 ,  H01L29/732 ,  H01L29/72

CPC分类号： H01L29/0813

摘要： This application describes a semiconductor device having a power amplifier pattern consisting of a plurality of parallel-connected transistor unit cells with emitters thereof being arrayed like meshes, wherein the width of the emitter of each transistor unit cell is not in excess of 50 microns. The limitation of the emitter width contributes to enhancement of the reverse-bias breakdown endurance.

摘要翻译： 本申请描述了一种具有功率放大器模式的半导体器件，该功率放大器模式由多个并联的晶体管单元电池组成，其发射极像网格一样排列，其中每个晶体管单电池的发射极的宽度不超过50微米。 发射极宽度的限制有助于提高反向偏压击穿耐力。

公开(公告)号：US5128823A

公开(公告)日：1992-07-07

申请号：US365765

申请日：1989-06-14

申请人： Hiroshi Fujimoto ,  Masami Yamaoka ,  Yukio Tsuzuki

发明人： Hiroshi Fujimoto ,  Masami Yamaoka ,  Yukio Tsuzuki

IPC分类号： H03K17/08

CPC分类号： H03K17/08

摘要： A power MOS transistor and a current sensing MOS transistor have a common drain electrode connected to a load. The gates of these MOS transistors are commonly controlled in response to an input control signal. A load current sensing resistor element is connected between the source electrodes of these transistors. A voltage signal sensed by the load sensing resistor element is amplified by a differential amplifier constituted by a pair of depletion type MOS transistors. The amplified output controls the MOS transistors, and the MOS transistors variably control a voltage of the input control signal to be supplied to the power and current sensing MOS transistors. The power MOS transistor, the current sensing MOS transistor, the depletion MOS transistor, the current control MOS transistor, and the like have the same conductivity type.

摘要翻译： 功率MOS晶体管和电流感测MOS晶体管具有连接到负载的公共漏电极。 这些MOS晶体管的栅极通常响应于输入控制信号来控制。 负载电流检测电阻元件连接在这些晶体管的源电极之间。 由负载感测电阻元件感测的电压信号由由一对耗尽型MOS晶体管构成的差分放大器放大。 放大的输出控制MOS晶体管，并且MOS晶体管可变地控制要提供给功率和电流感测MOS晶体管的输入控制信号的电压。 功率MOS晶体管，电流感测MOS晶体管，耗尽型MOS晶体管，电流控制MOS晶体管等具有相同的导电类型。

公开(公告)号：US4879254A

公开(公告)日：1989-11-07

申请号：US204375

申请日：1988-06-09

申请人： Yukio Tsuzuki ,  Masami Yamaoka

发明人： Yukio Tsuzuki ,  Masami Yamaoka

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/45 ,  H01L29/78

CPC分类号： H01L29/66712 ,  H01L29/7802 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/456 ,  Y10S148/103 ,  Y10S148/111 ,  Y10S148/126 ,  Y10S148/131

摘要： A method for manufacturing a DMOS which comprises forming a first conductive type layer on a substrate, forming a gate oxide layer thereon, forming a gate electrode layer and a second insulating layer successively on the gate oxide layer, forming a second conductive type body region and a first conductive type source region having a narrower width by implanting impurities utilizing the second insulating layer as a mask, forming a side wall spacer of an insulating material on at least a side portion of the gate electrode, forming a conductive passage penetrating the source region and extending into the body region while utilizing the second insulating layer and the side wall spacer as mask, optionally implanting the exposed body region, further excessively etching the sidewall spacer, the masking layer overlying the gate, and the gate oxide prior to providing an electrode connecting the source and body regions.

摘要翻译： 一种DMOS的制造方法，其特征在于，在基板上形成第一导电型层，在其上形成栅极氧化层，在所述栅极氧化层上依次形成栅电极层和第二绝缘层，形成第二导电型体区域， 通过使用第二绝缘层作为掩模注入杂质而具有较窄宽度的第一导电类型源极区域，在栅电极的至少一个侧部分上形成绝缘材料的侧壁隔离物，形成穿透源极区域的导电通路 并且在利用第二绝缘层和侧壁间隔物作为掩模的同时延伸到身体区域中，任选地植入暴露的身体区域，在提供电极之前进一步过度蚀刻侧壁间隔物，覆盖栅极的掩模层和栅极氧化物 连接源和身体区域。

公开(公告)号：US4672402A

公开(公告)日：1987-06-09

申请号：US912673

申请日：1986-09-25

申请人： Masami Yamaoka ,  Yukio Tsuzuki ,  Shoji Toyoshima

发明人： Masami Yamaoka ,  Yukio Tsuzuki ,  Shoji Toyoshima

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/866 ,  H01L29/868 ,  H01L29/90

CPC分类号： H01L29/868

摘要： In a semiconductor circuit device having a diode as an overvoltage protection element, a semiconductor substrate is comprised of an N-type collector substrate integral with a transistor. An N.sup.+ type collector diffusion layer is formed on the rear surface of the substrate. A P-type anode region and a N.sup.+ cathode region are formed in the major surface of the substrate so that they are spaced apart from each other and the N.sup.+ cathode region has the same type of impurity, but at a higher impurity concentration level than, the semiconductor substrate. An insulating film is formed on the surface of the resultant structure. A gate electrode is formed in an overlapping relation to the anode region and cathode region with an insulating film therebetween. A gate potential is established between the gate electrode and the underlying substrate.

摘要翻译： 在具有二极管作为过电压保护元件的半导体电路器件中，半导体衬底由与晶体管集成的N型集电极基板构成。 在基板的背面形成有N +型集电极扩散层。 在基板的主表面上形成P型阳极区域和N +阴极区域，使得它们彼此间隔开，并且N +阴极区域具有相同类型的杂质，但是在较高的杂质浓度水平下， 半导体衬底。 在所得结构的表面上形成绝缘膜。 与阳极区域和阴极区域之间具有绝缘膜的重叠关系形成栅电极。 在栅极电极和下面的衬底之间建立栅极电位。

公开(公告)号：US5136348A

公开(公告)日：1992-08-04

申请号：US647194

申请日：1991-01-28

申请人： Yukio Tsuzuki ,  Masami Yamaoka ,  Hiroshi Muto

发明人： Yukio Tsuzuki ,  Masami Yamaoka ,  Hiroshi Muto

IPC分类号： H01L27/06 ,  H01L27/12 ,  H01L29/04 ,  H01L29/78 ,  H01L29/861

CPC分类号： H01L29/7804 ,  H01L27/0688 ,  H01L27/12 ,  H01L29/04 ,  H01L29/861 ,  Y10S257/926

摘要： A structure and manufacturing method for a thin film semiconductor device consisting of a single diode or a plurality of diodes connected in series, the device being formed of at least one pair of mutually adjacent P-type (23a) and N-type (23b) regions formed in a layer of polycrystalline silicon (23) deposited on an insulating film (22) upon a substrate (21), to thereby define at least one PN junction. Each of the p-type regions and N-type regions is shaped as a rectangle, with opposite ends of each PN junction formed between these regions being respectively defined by two opposing sides of the polycrystalline silicon layer. Since each of the PN junctions is substantially rectilinear, an even distribution of current flow through each PN junction is attained, whereby a high resistance to destruction and an extremely stable value of reverse bias breakdown voltage are achieved.

摘要翻译： 一种由串联连接的单个二极管或多个二极管组成的薄膜半导体器件的结构和制造方法，该器件由至少一对相互相邻的P型（23a）和N型（23b）形成， 在衬底（21）上沉积在绝缘膜（22）上的多晶硅层（23）中形成的区域，从而限定至少一个PN结。 每个p型区域和N型区域被成形为矩形，其中形成在这些区域之间的每个PN结的相对端分别由多晶硅层的两个相对侧限定。 由于每个PN结基本上都是直线的，所以能够获得通过每个PN结的电流的平均分布，从而实现了高的抗破坏性和非常稳定的反向偏压击穿电压值。

公开(公告)号：US5264720A

公开(公告)日：1993-11-23

申请号：US879550

申请日：1992-05-04

申请人： Hiroshi Muto ,  Masami Yamaoka

发明人： Hiroshi Muto ,  Masami Yamaoka

IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L29/76

CPC分类号： H01L27/1203

摘要： A high withstanding voltage transistor is provided with a substrate with its main surface at least part of which is electrically insulated, and a plurality of MOS type field effect transistors of the same channel type that are formed on the insulated main surface of the substrate, the channel regions of the number of MOS type field effect transistors are electrically separated respectively, the gates of the plurality of MOS type field effect transistors are mutually connected electrically, between and among the plurality of MOS type field effect transistors, the source of one transistor is connected to the drain of another transistor, and connecting in series the plurality of MOS type field effect transistors, they are made into a single transistor, thereby dividing the voltage applied in between the drain and the source of this high withstanding voltage transistor with depletion layer of the respective transistors and in turn improving the withstanding voltage of the whole.

摘要翻译： 高耐压晶体管设置有其主表面的至少一部分是电绝缘的基板，以及形成在基板的绝缘主表面上的多个相同沟道类型的MOS型场效应晶体管， 多个MOS型场效应晶体管的通道区分别电分离，多个MOS型场效应晶体管的栅极电连接，在多个MOS型场效应晶体管之间和之间相互连接，一个晶体管的源极 连接到另一个晶体管的漏极，并串联连接多个MOS型场效应晶体管，将它们制成单个晶体管，从而将施加在该耐高压晶体管的漏极和源极之间的电压除以耗尽层 并进而改善整体的耐受电压。

公开(公告)号：US06949434B2

公开(公告)日：2005-09-27

申请号：US10880048

申请日：2004-06-29

申请人： Yoshifumi Okabe ,  Masami Yamaoka ,  Akira Kuroyanagi

发明人： Yoshifumi Okabe ,  Masami Yamaoka ,  Akira Kuroyanagi

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/304 ,  H01L21/336 ,  H01L29/06 ,  H01L29/167 ,  H01L29/34 ,  H01L29/417 ,  H01L29/45 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062 ,  H01L21/3205 ,  H01L21/44

CPC分类号： H01L29/7802 ,  H01L21/28 ,  H01L21/28512 ,  H01L21/304 ,  H01L29/0657 ,  H01L29/167 ,  H01L29/34 ,  H01L29/41741 ,  H01L29/456 ,  H01L29/66712 ,  H01L2924/0002 ,  H01L2924/10158 ,  Y10S148/135 ,  Y10S438/928 ,  Y10S438/938 ,  Y10S438/964 ,  Y10S438/977 ,  H01L2924/00

摘要： A method of manufacturing a vertical semiconductor device includes preparing a semiconductor wafer which has a heavily doped semiconductor substrate and a lightly doped semiconductor layer disposed over the semiconductor substrate, forming a semiconductor element at a surface portion of the semiconductor layer, forming a first metal layer for a first electrode of the semiconductor element over the surface portion of the semiconductor layer, grinding a back of the semiconductor substrate to thin the semiconductor substrate and roughen a back surface of the semiconductor substrate, performing a wet etching upon the back surface; and forming on the back surface a second metal layer for a second electrode of the semiconductor element.

摘要翻译： 一种制造垂直半导体器件的方法包括制备半导体晶片，该半导体晶片具有重掺杂半导体衬底和设置在半导体衬底上的轻掺杂半导体层，在半导体层的表面部分形成半导体元件，形成第一金属层 在半导体层的表面部分上的半导体元件的第一电极，研磨半导体衬底的背面以使半导体衬底细化并粗糙化半导体衬底的背面，对背面进行湿式蚀刻; 以及在所述背面上形成用于所述半导体元件的第二电极的第二金属层。

公开(公告)号：US5360765A

公开(公告)日：1994-11-01

申请号：US914623

申请日：1992-07-17

申请人： Ichiharu Kondo ,  Takao Yoneyama ,  Masami Yamaoka

发明人： Ichiharu Kondo ,  Takao Yoneyama ,  Masami Yamaoka

IPC分类号： H01L21/285 ,  H01L29/08

CPC分类号： H01L29/7802 ,  H01L21/28518 ,  H01L29/456 ,  H01L29/66712 ,  Y10S438/906

摘要： A method for forming electrodes with strong adhesion strength for a semiconductor device is provided. The adhesion strength between a Si substrate and a Ti film is made higher than the pulling stress of a Ni film. Before an electrode is formed using sputtering process, the natural oxide film grown on a semiconductor substrate is removed using an Ar reverse sputtering while the top surface of the silicon substrate is converted to an amorphous through a bombardment and introduction of Ar. While Ti is deposited, a Si-Ti amorphous layer is formed in the Si/Ti interface. In this case, the amount of Ar atoms is controlled less than 4.0.times.10.sup.14 atoms/cm.sup.2. The Ar amount also can be controlled by adjusting the conditions such as the output or cathodic voltage of Ar reverse sputtering and decreasing the absolute value of Ar in the amorphous Si layer. Also the Ar amount can be controlled by diffusing Ar atoms into the substrate at more than about 300.degree. C. during Ti film deposition to diverse the Ar distribution. As a result argon atoms which concentrates at the interface do not affect with respect to the Si-Ti amorphous layer, whereby the bonding strength of the amorphous layer is maintained. Therefore, the strong adhesion strength between Si and Ti can provide a sufficient durability against the film stress of the Ni film.

摘要翻译： 提供了一种用于形成用于半导体器件的具有强粘合强度的电极的方法。 使Si衬底和Ti膜之间的粘合强度高于Ni膜的拉伸应力。 在使用溅射法形成电极之前，使用Ar反溅射除去在半导体衬底上生长的天然氧化物膜，同时通过轰击和引入Ar将硅衬底的顶表面转化为无定形。 当沉积Ti时，在Si / Ti界面中形成Si-Ti非晶层。 在这种情况下，Ar原子的量控制在4.0×1014原子/ cm2以下。 Ar量也可以通过调节Ar逆溅射的输出或阴极电压等条件来降低非晶硅层中的绝对值Ar来控制。 此外，Ar量可以通过在Ti膜沉积期间将Ar原子扩散到基底中超过约300℃来控制，以使Ar分布变得多样化。 结果，在界面处浓缩的氩原子相对于Si-Ti非晶层不会受到影响，由此保持非晶层的结合强度。 因此，Si和Ti之间的强粘合强度可以提供足够的抗Ni膜的膜应力的耐久性。