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    Multi-level message passing descriptor
    1.
    发明授权
    Multi-level message passing descriptor 有权

    公开(公告)号：US10013373B1

    公开(公告)日：2018-07-03

    申请号：US15344537

    申请日：2016-11-06

    Applicant: BiTMICRO Networks, Inc.

    Inventor： Ricardo H. Bruce ,  Bernard Sherwin Leung Chiw ,  Margaret Anne Nadonga Somera

    IPC: G06F13/28 ,  G06F13/16

    CPC classification number: G06F13/28 ,  G06F13/1673 ,  G06F2213/2802

    Abstract: In an embodiment of the invention, a method for to use a two level linked list descriptor mechanism to pass information among flash, memory, and IO controller modules is presented. The method includes creating a first level data structure for one or more first level descriptors; creating a second level data structure for one or more second level descriptors, each second level descriptor having a pointer to tracking information that includes start information, running information, and rewind information for a data DMA; using the one or more second level descriptors, the one or more first level descriptors, and the tracking information for a data DMA; updating the tracking information during the data DMA; and updating the tracking information at the end of the data DMA.

    Multi-level message passing descriptor
    5.
    发明授权
    Multi-level message passing descriptor 有权
    多级消息传递描述符

    公开(公告)号：US09501436B1

    公开(公告)日：2016-11-22

    申请号：US14217041

    申请日：2014-03-17

    Applicant: BiTMICRO Networks, Inc.

    Inventor： Ricardo H. Bruce ,  Bernard Sherwin Leung Chiw ,  Margaret Anne Nadonga Somera

    IPC: G06F13/28

    CPC classification number: G06F13/28 ,  G06F13/1673 ,  G06F2213/2802

    Abstract: In an embodiment of the invention, a method for to use a two level linked list descriptor mechanism to pass information among flash, memory, and IO controller modules is presented. The method includes creating a first level data structure for one or more first level descriptors; creating a second level data structure for one or more second level descriptors, each second level descriptor having a pointer to tracking information that includes start information, running information, and rewind information for a data DMA; using the one or more second level descriptors, the one or more first level descriptors, and the tracking information for a data DMA; updating the tracking information during the data DMA; and updating the tracking information at the end of the data DMA.

    Abstract translation: 在本发明的实施例中，提出了一种使用二级链表描述符机制来在闪存，存储器和IO控制器模块之间传递信息的方法。 该方法包括为一个或多个第一级描述符创建第一级数据结构; 为一个或多个第二级描述符创建第二级数据结构，每个第二级描述符具有指向跟踪信息的指针，所述跟踪信息包括数据DMA的开始信息，运行信息和倒带信息; 使用一个或多个第二级描述符，一个或多个第一级描述符和数据DMA的跟踪信息; 在数据DMA期间更新跟踪信息; 并在数据DMA结束时更新跟踪信息。

    Multi-leveled cache management in a hybrid storage system
    7.
    发明授权
    Multi-leveled cache management in a hybrid storage system 有权
    混合存储系统中的多级缓存管理

    公开(公告)号：US09430386B2

    公开(公告)日：2016-08-30

    申请号：US14217436

    申请日：2014-03-17

    Applicant: BiTMICRO Networks, Inc.

    Inventor： Rolando H. Bruce ,  Elmer Paule Dela Cruz ,  Mark Ian Alcid Arcedera

    IPC: G06F12/08

    CPC classification number: G06F12/0811 ,  G06F12/0844 ,  G06F12/0868 ,  G06F2212/1016 ,  G06F2212/217 ,  G06F2212/225 ,  G06F2212/313

    Abstract: A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower. Methods provided here may be extended for systems that have more than two cache levels.

    Abstract translation: 描述了具有包括旋转驱动器，闪存装置，SDRAM和SRAM的不同类型的存储装置的混合的混合存储系统。 旋转驱动器用作主存储器，提供每单位存储存储器的最低成本。 闪存用作旋转驱动器的更高级缓存。 提供了用于管理该存储系统的多级缓存的方法，其具有由易失性存储器（SRAM或SDRAM）组成的非常快速的1级缓存以及使用闪存器件阵列的非易失性级别2高速缓存。 它描述了一种在旋转驱动器之间分配数据以使缓存更有效率的方法。 它还描述了将数据从L1高速缓存和L2高速缓存冲刷到旋转驱动器的有效技术，利用并发闪存设备操作，并发旋转驱动操作和最大化旋转驱动器中的顺序访问类型，而不是相对较慢的随机访问。 这里提供的方法可以扩展到具有两个以上缓存级别的系统。

    Self-test solution for delay locked loops
    8.
    发明授权
    Self-test solution for delay locked loops 有权
    用于延迟锁定环路的自检解决方案

    公开(公告)号：US09423457B2

    公开(公告)日：2016-08-23

    申请号：US14214216

    申请日：2014-03-14

    Applicant: Edzel Gerald Dela Cruz Raffiñan

    Inventor： Edzel Gerald Dela Cruz Raffiñan

    IPC: G01R31/02 ,  G01R25/00 ,  G01R31/317 ,  G11C29/02 ,  G11C29/50

    CPC classification number: G01R31/31725 ,  G01R31/31724 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12 ,  G11C29/50012

    Abstract: A built-in self test (BIST) circuit and method is provided to test a first and a second DLL. The first DLL has a first delay input, a first clock input disposed to receive a clock input signal, and a first clock output that provides a first clock output signal delayed in comparison with the clock input signal. The second DLL has a second delay input, a second clock input disposed to receive the clock input signal, and a second clock output signal delayed in comparison with the clock input signal. The BIST circuitry provides a first delay amount over the first delay input creating a start offset between the first and second clock output signals. If the first DLL is functioning properly the start offset between the output signals should remain unchanged even after the BIST circuitry provides an additional common delay amount to the first and second delay inputs.

    Abstract translation: 提供内置的自检（BIST）电路和方法来测试第一个和第二个DLL。 第一DLL具有第一延迟输入端，第一时钟输入端，用于接收时钟输入信号;以及第一时钟输出端，其提供与时钟输入信号相比延迟的第一时钟输出信号。 第二DLL具有第二延迟输入，第二时钟输入被设置为接收时钟输入信号，以及与时钟输入信号相比延迟的第二时钟输出信号。 BIST电路在第一延迟输入端提供第一延迟量，产生第一和第二时钟输出信号之间的起始偏移。 如果第一个DLL正常工作，即使在BIST电路为第一和第二延迟输入提供额外的公共延迟量之后，输出信号之间的起始偏移也应保持不变。

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