公开(公告)号：US07709310B2

公开(公告)日：2010-05-04

申请号：US12003559

申请日：2007-12-28

申请人： Kozo Markiyama ,  Naoya Ikechi ,  Takahiro Tan

发明人： Kozo Markiyama ,  Naoya Ikechi ,  Takahiro Tan

IPC分类号： H01L21/28 ,  H01L21/44 ,  H01L21/302 ,  H01L21/338

CPC分类号： H01L21/0274 ,  H01L21/28114 ,  H01L21/28264 ,  H01L21/28587 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66871 ,  H01L29/78 ,  Y10S430/143 ,  Y10S438/949 ,  Y10S438/95 ,  Y10S438/951

摘要： A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

摘要翻译： 半导体器件具有：半导体衬底，具有电流流过的一对电流输入/输出区域; 形成在所述半导体基板上并具有栅电极开口的绝缘膜; 以及通过所述栅电极开口形成在所述半导体基板上的蘑菇栅极电极结构，所述蘑菇栅电极结构具有杆和形成在所述杆上的头部，所述杆在所述半导体衬底上沿着电流方向具有有限的尺寸，并且具有 向前锥形形状向上并沿着电流方向单调地增加尺寸，头部具有沿着电流方向逐步扩大的尺寸，并且杆在栅极电极开口中接触半导体衬底并且在至少一个位置附近骑绝缘膜 杆的相对端之一沿着当前方向。

公开(公告)号：US07626443B2

公开(公告)日：2009-12-01

申请号：US12068275

申请日：2008-02-05

申请人： Takayaki Kitazawa ,  Naoyuki Miyazawa

发明人： Takayaki Kitazawa ,  Naoyuki Miyazawa

IPC分类号： H03K17/00

CPC分类号： H03K17/693 ,  Y10T307/74 ,  Y10T307/826

摘要： A switching circuit includes switching transistors connected to one of an input terminal and an output terminal of the switching circuit, and a control bias supply circuit that supplies a control bias for cutting off all the switching transistors to the switching transistors when all of the switching transistors are in a non-selected state.

摘要翻译： 开关电路包括连接到开关电路的输入端子和输出端子之一的开关晶体管，以及控制偏置电源电路，当所有开关晶体管都被提供给切换晶体管的所有开关晶体管的控制偏压 处于非选择状态。

公开(公告)号：US07105798B2

公开(公告)日：2006-09-12

申请号：US10665259

申请日：2003-09-22

申请人： Gang Wang ,  Yoshihiro Yoneda

发明人： Gang Wang ,  Yoshihiro Yoneda

IPC分类号： H01L31/00

CPC分类号： H01L27/1443 ,  H01L31/02019 ,  H01L31/105 ,  H01L31/107 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor light-receiving device includes: a substrate that has a first surface and a second surface facing each other; a first semiconductor layer that is formed on the first surface of the substrate and includes at least one semiconductor layer of a first conductivity type; a light absorption layer that is formed on the first semiconductor layer and generates carriers in accordance with incident light; a second semiconductor layer that is formed on the light absorption layer and includes at least one semiconductor layer of a second conductivity type; a first electrode part that is electrically connected to the first semiconductor layer and applies a first potential thereto; a second electrode part that is electrically connected to the second semiconductor layer and applies a second potential thereto; and a third semiconductor layer of the second conductivity type that is interposed between the first surface of the substrate and the first semiconductor layer.

摘要翻译： 半导体光接收装置包括：具有彼此面对的第一表面和第二表面的基板; 第一半导体层，其形成在所述基板的所述第一表面上，并且包括至少一个第一导电类型的半导体层; 形成在第一半导体层上并根据入射光产生载流子的光吸收层; 第二半导体层，其形成在所述光吸收层上并且包括至少一个第二导电类型的半导体层; 电连接到第一半导体层并向其施加第一电位的第一电极部分; 电连接到第二半导体层并向其施加第二电位的第二电极部分; 以及介于基板的第一表面和第一半导体层之间的第二导电类型的第三半导体层。

公开(公告)号：US06975031B2

公开(公告)日：2005-12-13

申请号：US10060323

申请日：2002-02-01

申请人： Hiromitsu Kawamura

发明人： Hiromitsu Kawamura

IPC分类号： H01L23/34 ,  G01K7/22 ,  H01S5/02 ,  H01S5/022 ,  H01S5/024 ,  H01L23/48 ,  H01C7/10 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01S5/02276 ,  G01K7/22 ,  G01K7/226 ,  H01L2224/45144 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01S5/02248 ,  H01S5/02272 ,  H01S5/02284 ,  H01S5/02415 ,  H01S5/02438 ,  H01S5/06804 ,  H01L2924/00

摘要： There are provided a carrier substrate, a temperature sensing resistor film formed directly on the carrier substrate, first and second conductive patterns formed on the carrier substrate and connected to both ends of the temperature sensing resistor film respectively, and a semiconductor chip mounting region portion formed on the carrier substrate.

摘要翻译： 提供了载体基板，直接形成在载体基板上的温度感测电阻膜，分别形成在载体基板上并连接到温度感测电阻膜的两端的第一和第二导电图案，以及半导体芯片安装区域部分 在载体衬底上。

公开(公告)号：US06944252B2

公开(公告)日：2005-09-13

申请号：US09956880

申请日：2001-09-21

申请人： Masaaki Okamoto

发明人： Masaaki Okamoto

IPC分类号： H03K5/26 ,  H03D13/00 ,  H03L7/089 ,  H03D3/24

CPC分类号： H03D13/004

摘要： A data signal DATA is captured by flip-flops 10 and 11 alternately every half cycle time of a clock signal CLK, outputs of the flip-flops 10 and 11 are delayed by respective delay circuits 15 and 16 to generate delayed signals 10QD and 11QD, and an output of the flip-flop 10 and the delayed signal 11QD are provided to an XOR gate 18, while an output of the flip-flop 11 and the delayed signal 10QD are provided to an XOR gate 17. The delay times of the delay circuits may be variable. Furthermore, outputs of the XOR gates 17 and 18 may be captured by the respective flip-flops alternately every half-cycle time of a delayed clock signal obtained by delaying the clock signal CLK.

摘要翻译： 数据信号DATA由时钟信号CLK的每半周期交替地由触发器10和11捕获，触发器10和11的输出被相应的延迟电路15和16延迟，以产生延迟信号10QD和11 QD，并且触发器10和延迟信号11QD的输出被提供给异或门18，而触发器11的输出和延迟信号10QD被提供给异或门17。 延迟电路的延迟时间可以是可变的。 此外，XOR门17和18的输出可以由延迟时钟信号CLK获得的延迟时钟信号的每半周期交替地由各个触发器捕获。

公开(公告)号：US06900482B2

公开(公告)日：2005-05-31

申请号：US10096856

申请日：2002-03-14

申请人： Yoshio Aoki ,  Yutaka Mimino ,  Osamu Baba ,  Muneharu Gotoh

发明人： Yoshio Aoki ,  Yutaka Mimino ,  Osamu Baba ,  Muneharu Gotoh

IPC分类号： H01L21/338 ,  H01L29/06 ,  H01L29/423 ,  H01L29/80 ,  H01L29/812 ,  H01L29/76 ,  H01L31/112

CPC分类号： H01L29/42316 ,  H01L29/0692 ,  H01L29/802

摘要： A high-frequency semiconductor device for power amplification has a comb-teeth electrode on each of active regions formed on the front surface of the semiconductor substrate. One aspect of the present invention, there is provided a monolithic microwave integrated circuit (MMIC) having a plurality of rectangular-shaped active regions arranged side by side on the front surface of the semiconductor substrate, each of the active regions having interdigited gate, drain and source electrodes thereon which are connected to the respective pads by multilayer interconnection technique. Additionally, the source potential is fed from the back surface of the substrate through a metal plugged via-hole.

摘要翻译： 用于功率放大的高频半导体器件在形成在半导体衬底的前表面上的每个有源区上具有梳齿电极。 本发明的一个方面提供了一种单片式微波集成电路（MMIC），其具有在半导体衬底的前表面上并排布置的多个矩形有源区，每个有源区具有交叉的栅极，漏极 和其上的源电极，其通过多层互连技术连接到相应的焊盘。 此外，源电位通过金属堵塞的通孔从衬底的背面进给。

公开(公告)号：US06853054B2

公开(公告)日：2005-02-08

申请号：US10078346

申请日：2002-02-21

申请人： Osamu Baba ,  Yutaka Mimino

发明人： Osamu Baba ,  Yutaka Mimino

IPC分类号： H01L21/768 ,  H01L21/82 ,  H01L21/822 ,  H01L23/522 ,  H01L23/552 ,  H01L23/66 ,  H01L27/04 ,  H01P3/08 ,  H01L23/58

CPC分类号： H01L23/5222 ,  H01L23/5225 ,  H01L23/552 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A high frequency semiconductor device including wiring layers which are formed above a semiconductor substrate and in which transmission lines are formed by combining with a ground plate having a potential fixed at the ground potential, at least one crossing portion in which the wiring layers mutually cross, with insulating interlayers provided therebetween, and at least one separation electrode being selectively provided on one of the insulating interlayers, the at least one separation electrode having a potential fixed at the ground potential. Accordingly, in the high frequency semiconductor device, electrical interference between two crossing wiring layer is prevented and transmission loss is suppressed.

摘要翻译： 一种高频半导体器件，包括形成在半导体衬底上的布线层，其中传输线通过与固定在接地电位的电位的接地板组合而形成，所述布线层相互交叉的至少一个交叉部分， 其中设置有绝缘夹层，并且至少一个分离电极选择性地设置在绝缘夹层之一上，所述至少一个分离电极具有固定在地电位的电位。 因此，在高频半导体装置中，防止了两个交叉布线层之间的电干扰，并抑制了传输损耗。

公开(公告)号：US20040052491A1

公开(公告)日：2004-03-18

申请号：US10660746

申请日：2003-09-12

申请人： FUJITSU QUANTUM DEVICES LIMITED ,  FUJITSU LIMITED

发明人： Fumio Otake ,  Haruhisa Soda

IPC分类号： G02B006/10

CPC分类号： G02F1/2257 ,  G02B2006/12142

摘要： An optical modulator includes a p- or n-type semiconductor layer that is provided at an upper part of an optical waveguide path, and modulating electrodes that are provided at intervals on the semiconductor layer in an extension area of the optical waveguide path. The semiconductor layer has first regions located immediately under the modulating electrodes, and second regions located between the first regions. The second regions have separators that electrically separate the first regions from one another.

摘要翻译： 光调制器包括设置在光波导路径的上部的p型或n型半导体层，以及在光波导路径的扩展区域中在半导体层上间隔设置的调制电极。 半导体层具有位于调制电极正下方的第一区域和位于第一区域之间的第二区域。 第二区域具有将第一区域彼此电分离的隔板。

公开(公告)号：US20040000965A1

公开(公告)日：2004-01-01

申请号：US10463447

申请日：2003-06-18

申请人： FUJITSU QUANTUM DEVICES LIMITED

发明人： Kunihiro Usami ,  Toshiaki Moriuchi

IPC分类号： H01P005/18

CPC分类号： H01P5/185

摘要： A directional coupler includes a transmission line, and a coupling line, the transmission line being coupled with the coupling line. The transmission line is located at a height position different from that of the coupling line with respect to a reference plane. The transmission line and the coupling line have portions that do not overlap each other.

摘要翻译： 定向耦合器包括传输线和耦合线，传输线与耦合线耦合。 传输线位于相对于参考平面与耦合线不同的高度位置处。 传输线和耦合线具有彼此不重叠的部分。

公开(公告)号：US20030183846A1

公开(公告)日：2003-10-02

申请号：US10347694

申请日：2003-01-22

申请人： FUJITSU QUANTUM DEVICES LIMITED

发明人： Hiroyuki Oguri

IPC分类号： H01L031/0328 ,  H01L031/0336 ,  H01L031/072

CPC分类号： H01L29/66318 ,  H01L29/0817 ,  H01L29/7371

摘要： A hetero-junction bipolar transistor includes a collector layer, a base layer and an emitter layer, an emitter electrode containing Au being provided for the emitter layer, and an Au-diffusion barrier layer of InP or InGaP interposed between the emitter electrode and the base layer.

摘要翻译： 异质结双极晶体管包括集电极层，基极层和发射极层，为发射极层提供包含Au的发射极，以及置于发射极和基极之间的InP或InGaP的Au扩散阻挡层 层。