公开(公告)号：US20240363762A1

公开(公告)日：2024-10-31

申请号：US18769998

申请日：2024-07-11

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yong-Jie Wu ,  Hui-Hsien Wei ,  Yen-Chung Ho ,  Mauricio Manfrini ,  Chia-Jung Yu ,  Chung-Te Lin ,  Pin-Cheng Hsu

IPC分类号： H01L29/786 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/78696 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/7869

摘要： A semiconductor device includes a first dielectric layer, a gate electrode embedded within the first dielectric layer, a layer stack including a gate dielectric layer, a channel layer including a semiconducting metal oxide material, and a second dielectric layer, and a source electrode and a drain electrode embedded in the second dielectric layer and contacting a respective portion of a top surface of the channel layer. A combination of the gate electrode, the gate dielectric layer, the channel layer, the source electrode, and the drain electrode forms a transistor. The total length of the periphery of a bottom surface of the channel layer that overlies the gate electrode is equal to the width of the gate electrode or twice the width of the gate electrode, and resputtering of the gate electrode material on sidewalls of the channel layer is minimized.

公开(公告)号：US20240363565A1

公开(公告)日：2024-10-31

申请号：US18768080

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jen-Yuan CHANG

IPC分类号： H01L23/00 ,  H01L21/66 ,  H01L25/065

CPC分类号： H01L24/06 ,  H01L22/32 ,  H01L24/03 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/031 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06505 ,  H01L2224/06515 ,  H01L2224/08146 ,  H01L2224/80001

摘要： A semiconductor package structure includes a first die, a second die disposed on the first die, and a bonding pad structure. The first die includes a semiconductor substrate, an interconnect structure disposed on the first semiconductor substrate, a passivation layer disposed on the interconnect structure, and a test pad disposed on the passivation layer. The test pad includes a contact region that extends through the passivation layer and electrically contacts the interconnect structure, and a bonding recess that overlaps with the contact region in a vertical direction perpendicular to a plane of the first semiconductor substrate. The bonding pad structure electrically connects the first die and the second die and directly contacts at least a portion of the bonding recess.

公开(公告)号：US20240363344A1

公开(公告)日：2024-10-31

申请号：US18770783

申请日：2024-07-12

申请人： Taiwan Semiconductor Manufacturing Company Limited ,  National Chiao-Tung University

发明人： Hung-Wei Yu ,  Yi Chang ,  Tsun-Ming Wang

IPC分类号： H01L21/02 ,  H01L29/10 ,  H01L29/205 ,  H01L29/778

CPC分类号： H01L21/0262 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02546 ,  H01L21/02549 ,  H01L29/1033 ,  H01L29/205 ,  H01L29/7781

摘要： Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.

公开(公告)号：US12131915B2

公开(公告)日：2024-10-29

申请号：US18325905

申请日：2023-05-30

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jheng-Hong Jiang ,  Chia-Wei Liu ,  Shing-Huang Wu

IPC分类号： H01L21/321 ,  C22C21/12 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/3212 ,  C22C21/12 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53219 ,  H01L23/53223

摘要： A cavity may be formed in a dielectric material layer overlying a substrate. A layer stack including a metallic barrier liner, a metallic fill material layer, and a metallic capping material may be deposited in the cavity and over the dielectric material layer. Portions of the layer stack located above a horizontal plane including a top surface of the dielectric material layer may be removed. A contiguous set of remaining material portions of the layer stack includes a metal interconnect structure that is free of a pitted surface.

公开(公告)号：US20240357834A1

公开(公告)日：2024-10-24

申请号：US18757705

申请日：2024-06-28

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Bo-Feng Young ,  Yu-Ming Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Sai-Hooi Yeong

IPC分类号： H10B53/30 ,  H01L29/66 ,  H01L29/78 ,  H10B53/00 ,  H10B53/20

CPC分类号： H10B53/30 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/7841 ,  H10B53/00 ,  H10B53/20

摘要： A gated ferroelectric memory cell includes a dielectric material layer disposed over a substrate, a metallic bottom electrode, a ferroelectric dielectric layer contacting a top surface of the bottom electrode, a pillar semiconductor channel overlying the ferroelectric dielectric layer and capacitively coupled to the metallic bottom electrode through the ferroelectric dielectric layer, a gate dielectric layer including a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the pillar semiconductor channel, a gate electrode strip overlying the horizontal gate dielectric portion and laterally surrounding the tubular gate dielectric portion and a metallic top electrode contacting a top surface of the pillar semiconductor channel.

公开(公告)号：US12119266B2

公开(公告)日：2024-10-15

申请号：US18142142

申请日：2023-05-02

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Kuo-Cheng Ching ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu

IPC分类号： H01L21/82 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L21/823462 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/66795 ,  H01L29/517 ,  H01L29/518

摘要： A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer.

公开(公告)号：US12113099B2

公开(公告)日：2024-10-08

申请号：US18359023

申请日：2023-07-26

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Fu-Chiang Kuo

IPC分类号： H01G4/35 ,  H01L23/532 ,  H01L49/02 ,  H01L21/285 ,  H01L29/94

CPC分类号： H01L28/60 ,  H01G4/35 ,  H01L21/2855 ,  H01L23/5329 ,  H01L28/91 ,  H01L29/945

摘要： A deep trench is formed in a substrate. A layer stack including at least three metallic electrode layers interlaced with at least two node dielectric layers is formed over the substrate. The layer stack continuously extends into the deep trench, and a cavity is present in an unfilled volume of the deep trench. A dielectric fill material layer including a dielectric fill material is formed in the cavity and over the substrate. The dielectric fill material layer encapsulates a void that is free of any solid phase and is formed within a volume of the cavity. The void may expand or shrink under stress during subsequently handling of a deep trench capacitor including the layer stack to absorb mechanical stress and to increase mechanical stability of the deep trench capacitor.

公开(公告)号：US12113034B2

公开(公告)日：2024-10-08

申请号：US18138865

申请日：2023-04-25

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chien-Hsuan Liu

IPC分类号： H01L23/58 ,  H01L21/768 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/585 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/5226 ,  H01L23/5283

摘要： A semiconductor arrangement is provided. The semiconductor arrangement includes a first portion and a vertically conductive structure. The first portion includes a first dielectric layer and a first guard ring in the first dielectric layer. The first guard ring includes, in the first dielectric layer, a first metal layer coupled to a first via. The first portion includes a vertical conductive structure passing through the first dielectric layer and proximate by the first guard ring.

公开(公告)号：US20240321891A1

公开(公告)日：2024-09-26

申请号：US18679004

申请日：2024-05-30

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Shih-Yao Lin ,  Chih-Han Lin ,  Ming-Ching Chang ,  Shu-Yuan Ku ,  Tzu-Chung Wang

IPC分类号： H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/0924 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7851

摘要： A semiconductor device includes a substrate. The semiconductor device includes a dielectric fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric fin. The semiconductor device includes a gate structure extending along a second direction perpendicular to the first direction. The gate structure includes a first portion and a second portion separated by the gate isolation structure and the dielectric fin. The first portion of the gate structure presents a first beak profile and the second portion of the gate structure presents a second beak profile. The first and second beak profiles point toward each other.

公开(公告)号：US20240321772A1

公开(公告)日：2024-09-26

申请号：US18124752

申请日：2023-03-22

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yu Chen Lee ,  Chin-Hua Wang ,  Shin-Puu Jeng

IPC分类号： H01L23/00 ,  H01L23/538

CPC分类号： H01L23/562 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125

摘要： An embodiment semiconductor package includes an interposer, a first semiconductor die electrically coupled to a first side of the interposer, and a first reinforcement structure that is mechanically coupled to the interposer and to the first semiconductor die, such that the first reinforcement structure is a solid structure that is adhered to the interposer and to the first semiconductor die and includes an adhesive strength that is greater than 5 N/mm2 and less than 10 N/mm2. The first reinforcement structure is formed at a corner or at an edge of the first semiconductor die and may have a modulus that is greater than 0.1 GPa and less than 1.0 GPa. The semiconductor package may further include a second semiconductor die electrically coupled to the first side of the interposer and a second reinforcement structure that is mechanically coupled to the interposer and to the second semiconductor die.