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公开(公告)号:US20200083240A1
公开(公告)日:2020-03-12
申请号:US16684123
申请日:2019-11-14
发明人: Takehiko AMAKI , Yoshihisa KOJIMA , Toshikatsu HIDA , Marie Grace Izabelle Ange SIA , Riki SUZUKI , Shohei ASAMI
IPC分类号: H01L27/11556 , G11C16/10 , G11C16/08 , H01L27/11582 , H01L27/1157 , G11C16/26 , G11C7/04 , G11C16/16 , G11C16/04
摘要: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.
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公开(公告)号:US20210183877A1
公开(公告)日:2021-06-17
申请号:US17182879
申请日:2021-02-23
发明人: Takehiko AMAKI , Yoshihisa KOJIMA , Toshikatsu HIDA , Marie Grace Izabelle Angeles SIA , Riki SUZUKI , Shohei ASAMI
IPC分类号: H01L27/11556 , G11C16/08 , G11C16/10 , G11C16/04 , G11C16/16 , G11C7/04 , G11C16/26 , H01L27/1157 , H01L27/11582
摘要: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.
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公开(公告)号:US20180107413A1
公开(公告)日:2018-04-19
申请号:US15786959
申请日:2017-10-18
发明人: Riki SUZUKI , Toshikatsu HIDA , Takehiko AMAKI , Shunichi IGAHARA
IPC分类号: G06F3/06 , G06F12/0875 , G06F11/10 , G11C29/52
CPC分类号: G06F3/0619 , G06F3/0616 , G06F3/0634 , G06F3/0635 , G06F3/0656 , G06F3/0658 , G06F3/0679 , G06F11/1048 , G06F11/1068 , G06F12/0246 , G06F12/0875 , G06F2212/1032 , G06F2212/2022 , G06F2212/45 , G06F2212/7203 , G11C29/52 , G11C29/74 , G11C29/78
摘要: A memory system includes a nonvolatile semiconductor memory including a first memory region for storing start-up information and a second memory region for storing a copy of the start-up information, a volatile semiconductor memory, and a controller. The controller is configured to determine whether or not an address of the second memory region is stored in the volatile semiconductor memory, issue a first start-up read command, which designates no read address, to the nonvolatile semiconductor memory to read the start-up information from the first memory region if the address of the second memory region is not stored in the volatile semiconductor memory, and issue a second start-up read command, which designates the address of the second memory region as a read address, to read the start-up information from the second memory region if the address of the second memory region is stored in the volatile semiconductor memory.
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公开(公告)号:US20190332285A1
公开(公告)日:2019-10-31
申请号:US16506475
申请日:2019-07-09
发明人: Riki SUZUKI , Toshikatsu HIDA , Takehiko AMAKI , Shunichi IGAHARA
摘要: A memory system includes a nonvolatile semiconductor memory including a first memory region for storing start-up information and a second memory region for storing a copy of the start-up information, a volatile semiconductor memory, and a controller. The controller is configured to determine whether or not an address of the second memory region is stored in the volatile semiconductor memory, issue a first start-up read command, which designates no read address, to the nonvolatile semiconductor memory to read the start-up information from the first memory region if the address of the second memory region is not stored in the volatile semiconductor memory, and issue a second start-up read command, which designates the address of the second memory region as a read address, to read the start-up information from the second memory region if the address of the second memory region is stored in the volatile semiconductor memory.
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公开(公告)号:US20190094927A1
公开(公告)日:2019-03-28
申请号:US16010680
申请日:2018-06-18
发明人: Yuka KUWANO , Takehiko AMAKI , Toshikatsu HIDA , Shohei ASAMI
摘要: A memory system includes a nonvolatile memory and a memory controller. The memory controller is configured to execute a process to adjust a temperature of the nonvolatile memory upon determining that the temperature is outside a preferred range.
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公开(公告)号:US20190074283A1
公开(公告)日:2019-03-07
申请号:US16052238
申请日:2018-08-01
发明人: Takehiko AMAKI , Yoshihisa Kojima , Toshikatsu Hida , Marie Sia , Riki Suzuki , Shohei Asami
IPC分类号: H01L27/11556 , G11C16/10 , G11C16/08
CPC分类号: H01L27/11556 , G11C7/04 , G11C16/0483 , G11C16/08 , G11C16/107 , G11C16/16 , G11C16/26 , H01L27/1157 , H01L27/11582
摘要: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.
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公开(公告)号:US20190295658A1
公开(公告)日:2019-09-26
申请号:US16166409
申请日:2018-10-22
发明人: Takehiko AMAKI , Riki Suzuki , Yoshihisa Kojima
摘要: According to one embodiment, a memory system comprises a nonvolatile memory, and a memory controller configured to manage a history value about setting of a read voltage in performing reading of data from the nonvolatile memory, in accordance with a first management unit and a second management unit, a size of the second management unit being smaller than a size of the first management unit. A first region of the nonvolatile memory corresponds to the first management unit. A plurality of second regions of the nonvolatile memory each correspond to the second management unit. The first region includes the plurality of second regions. The controller is configured to: obtain a first history value for the first region, and obtain a second history value for at least one of the second regions; and in execution of a read operation to a region included in the second regions, when the second history value for the region included in the second regions is not obtained, execute the read operation to the region included in the second regions by using the first history value obtained for the first region.
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公开(公告)号:US20170364309A1
公开(公告)日:2017-12-21
申请号:US15692449
申请日:2017-08-31
发明人: Takehiko AMAKI , Riki SUZUKI , Toshikatsu HIDA
IPC分类号: G06F3/06 , G06F11/10 , G11C11/56 , G11C16/26 , G11C16/08 , G11C13/00 , G11C29/02 , G11C29/42 , G11C29/04 , G11C29/52
CPC分类号: G06F3/0679 , G06F3/0619 , G06F3/064 , G06F11/1048 , G11C11/5642 , G11C13/004 , G11C16/08 , G11C16/26 , G11C29/021 , G11C29/028 , G11C29/42 , G11C29/52 , G11C2013/0057 , G11C2029/0411 , G11C2211/5644
摘要: According to one embodiment, a memory controller of a memory system includes a command issuing unit, a decoder, a counter, and a statistical processor. The command issuing unit issues a first command for single read of first data from a nonvolatile memory. The decoder performs first error correction on the read first data. The counter counts a number of times of multiple reads. The statistical processor performs statistical processing of results of the multiple reads, and outputs second data obtained by the statistical processing. When the decoder is unable to perform the first error correction on the read first data, the command issuing unit issues a second command for multiple reads of the first data.
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公开(公告)号:US20210020253A1
公开(公告)日:2021-01-21
申请号:US17060767
申请日:2020-10-01
摘要: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.
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公开(公告)号:US20200073592A1
公开(公告)日:2020-03-05
申请号:US16280994
申请日:2019-02-20
摘要: A memory system includes a nonvolatile memory including a plurality of blocks, in each of which a plurality of memory cells is arranged between bit lines and a source line, and a memory controller configured to control an operation of the nonvolatile memory. The memory controller is configured to issue a warming command to the nonvolatile memory when a temperature of the nonvolatile memory is lower than a first temperature, and the nonvolatile memory, in response to the warming command, causes current to flow through at least one bit line connected to memory cells of a first block.
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