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1.发明公开公开(公告)号：US20240362023A1
公开(公告)日：2024-10-31
申请号：US18227707
申请日：2023-07-28
CPC分类号： G06F9/3016 , G06F9/3802
摘要： An example apparatus includes example packet decode circuitry to decode an instruction packet for programmable circuitry into at least one instruction. Additionally, the example apparatus includes example instruction mapping circuitry to disregard a pad instruction included in the at least one instruction, the pad instruction having not been assigned to any functional unit of the programmable circuitry.
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公开(公告)号：US20240354608A1
公开(公告)日：2024-10-24
申请号：US18352006
申请日：2023-07-13
CPC分类号： G06N10/00 , B82Y10/00 , G06F9/3877 , G06F9/5027 , H01J49/422 , H04B10/70 , H04L9/0858
摘要： The disclosure describes aspects of using multiple species in trapped-ion nodes for quantum networking. In an aspect, a quantum networking node is described that includes multiple memory qubits, each memory qubit being based on a 171Yb+ atomic ion, and one or more communication qubits, each communication qubit being based on a 138Ba+ atomic ion. The memory and communication qubits are part of a lattice in an atomic ion trap. In another aspect, a quantum computing system having a modular optical architecture is described that includes multiple quantum networking nodes, each quantum networking node including multiple memory qubits (e.g., based on a 171Yb+ atomic ion) and one or more communication qubits (e.g., based on a 138Ba+ atomic ion). The memory and communication qubits are part of a lattice in an atomic ion trap. The system further includes a photonic entangler coupled to each of the multiple quantum networking nodes.
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公开(公告)号：US20240354260A1
公开(公告)日：2024-10-24
申请号：US18762987
申请日：2024-07-03
IPC分类号： G06F12/1045 , G06F7/24 , G06F7/487 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/30 , G06F9/32 , G06F9/345 , G06F9/38 , G06F9/48 , G06F11/00 , G06F11/10 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F15/78 , G06F17/16 , H03H17/06
CPC分类号： G06F12/1045 , G06F7/24 , G06F7/487 , G06F7/4876 , G06F7/49915 , G06F7/53 , G06F7/57 , G06F9/3001 , G06F9/30014 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30072 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/3818 , G06F9/383 , G06F9/3836 , G06F9/3851 , G06F9/3856 , G06F9/3867 , G06F9/3887 , G06F9/48 , G06F11/00 , G06F11/1048 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F17/16 , H03H17/0664 , G06F9/30018 , G06F9/325 , G06F9/381 , G06F9/3822 , G06F11/10 , G06F15/7807 , G06F15/781 , G06F2212/452 , G06F2212/60 , G06F2212/602 , G06F2212/68
摘要： A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values are sorted in an order indicated by the vector sort instruction, and storing the sorted vector in a storage location.
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公开(公告)号：US20240354107A1
公开(公告)日：2024-10-24
申请号：US18754447
申请日：2024-06-26
申请人： Intel Corporation
CPC分类号： G06F9/30047 , G06F9/321 , G06F9/3836
摘要： In one example, a processor includes: at least one core to execute instructions; and at least one cache memory coupled to the at least one core, the at least one cache memory to store data, at least some of the data a copy of data stored in a memory. The at least one core is to determine whether to conditionally offload a sequence of instructions for execution on a compute circuit associated with the memory, based at least in part on whether one or more first data is present in the at least one cache memory, the one or more first data for use during execution of the sequence of instructions. Other embodiments are described and claimed.
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公开(公告)号：US12124455B2
公开(公告)日：2024-10-22
申请号：US18331833
申请日：2023-06-08
IPC分类号： G06F15/16 , G06F9/38 , G06F12/02 , G06F16/22 , G06F16/2455 , G06F16/28 , H04L67/1097 , H04L67/568 , H04L67/2885
CPC分类号： G06F16/24553 , G06F9/3834 , G06F12/0261 , G06F16/22 , G06F16/24552 , G06F16/24562 , G06F16/284 , H04L67/1097 , H04L67/568 , H04L67/2885
摘要： Systems and methods for managing concurrent access to a shared resource in a distributed computing environment are provided. A reference counter counts is incremented for every use of an object subtype in a session and decremented for every release of an object subtype in a session. A session counter is incremented upon the first instance of fetching an object type into a session cache and decremented upon having no instances of the object type in use in the session. When both the reference counter and the session counter are zero, the object type may be removed from the cache.
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6.发明公开公开(公告)号：US20240345842A1
公开(公告)日：2024-10-17
申请号：US18754455
申请日：2024-06-26
CPC分类号： G06F9/383 , G06F9/30036 , G06F9/3004 , G06F9/30043
摘要： This disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.
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公开(公告)号：US12118641B2
公开(公告)日：2024-10-15
申请号：US17482198
申请日：2021-09-22
发明人： Mark E. Cerny , Tobias Berghoff , David Simpson
CPC分类号： G06T1/20 , G06F9/3877 , G06F9/5027 , G06T15/005 , G06T15/10 , G06T17/10
摘要： A method for graphics processing. The method including rendering graphics for an application using a plurality of graphics processing units (GPUs). The method including using the plurality of GPUs in collaboration to render an image frame including a plurality of pieces of geometry. The method including during a pre-pass phase of rendering, generating information at the GPUs regarding the plurality of pieces of geometry and their relation to a plurality of screen regions. The method including assigning the plurality of screen regions to the plurality of GPUs based on the information for purposes of rendering the plurality of pieces of geometry in a subsequent phase of rendering.
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8.发明授权公开(公告)号：US12118391B2
公开(公告)日：2024-10-15
申请号：US18151946
申请日：2023-01-09
CPC分类号： G06F9/5005 , G06F9/3836 , G06F9/48
摘要： A system for allocation of resources and processing jobs within a distributed system includes a processor and a memory coupled to the processor. The memory includes at least one process and at least one resource allocator. The process is adapted for processing jobs within a distributed system which receives jobs to be processed. The resource allocator is communicably coupled with at least one process, and is adapted to generate one or more sub-processes within a limit of one or more resources allocated to the process for processing jobs.
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公开(公告)号：US12118358B2
公开(公告)日：2024-10-15
申请号：US17583380
申请日：2022-01-25
IPC分类号： G06F9/30 , G06F9/32 , G06F9/345 , G06F9/38 , G06F11/00 , G06F11/10 , G06F12/0811 , G06F12/0875 , G06F12/0897 , G06F15/80 , G06F17/16
CPC分类号： G06F9/3016 , G06F9/30014 , G06F9/30036 , G06F9/30043 , G06F9/30098 , G06F9/30101 , G06F9/30112 , G06F9/30145 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/383 , G06F9/3867 , G06F11/00 , G06F11/1048 , G06F12/0811 , G06F12/0875 , G06F12/0897 , G06F15/8015 , G06F9/3822 , G06F11/10 , G06F17/16 , G06F2212/452 , G06F2212/60 , G06F2212/604
摘要： Software instructions are executed on a processor within a computer system to configure a streaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array and a specified width for a selected dimension of the array. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. When the selected dimension in the stream of vectors exceeds the specified width, the streaming engine inserts null elements into each portion of a respective vector for the selected dimension that exceeds the specified width in the stream of vectors. Stream vectors that are completely null are formed by the streaming engine without accessing the system memory for respective data.
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公开(公告)号：US20240338220A1
公开(公告)日：2024-10-10
申请号：US18603171
申请日：2024-03-12
申请人： Simplex Micro, Inc.
发明人： Thang Minh Tran
CPC分类号： G06F9/3806 , G06F9/30058 , G06F9/3856
摘要： A processor includes a branch execution unit to detect different loop types based on the number of instructions in the loop and generates a predicted loop count to write to an entry of a branch target buffer (BTB). The different detected loop types are executed in a plurality of instruction queues in the processor depending on the loop type, which is a function of the loop size.
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