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    Dual-damascene metal wiring patterns for integrated circuit devices
    4.
    发明授权
    Dual-damascene metal wiring patterns for integrated circuit devices 有权
    用于集成电路器件的双镶嵌金属布线图案

    公开(公告)号：US07550822B2

    公开(公告)日：2009-06-23

    申请号：US11421202

    申请日：2006-05-31

    申请人： Boung Ju Lee ,  Heon Jong Shin ,  Hee Sung Kang

    发明人： Boung Ju Lee ,  Heon Jong Shin ,  Hee Sung Kang

    IPC分类号： H01L21/10

    CPC分类号： H01L21/76832 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of forming dual-damascene metal wiring patterns include forming a first metal wiring pattern (e.g., copper wiring pattern) on an integrated circuit substrate and forming an etch-stop layer on the first metal wiring pattern. These steps are followed by the steps of forming an electrically insulating layer on the etch-stop layer and forming an inter-metal dielectric layer on the electrically insulating layer. The inter-metal dielectric layer and the electrically insulating layer are selectively etched in sequence to define an opening therein that exposes a first portion of the etch-stop layer. This opening may include a trench and a via hole extending downward from a bottom of the trench. A first barrier metal layer is formed on a sidewall of the opening and directly on the first portion of the etch-stop layer. A portion of the first barrier metal layer is selectively removed from the first portion of the etch-stop layer. The first portion of the etch-stop layer is then selectively etched for a sufficient duration to expose a portion of the first metal wiring pattern. A second metal wiring pattern is formed in the opening in order to complete a dual-damascene structure.

    摘要翻译： 形成双镶嵌金属布线图案的方法包括在集成电路基板上形成第一金属布线图案（例如铜布线图案），并在第一金属布线图案上形成蚀刻停止层。 这些步骤之后是在蚀刻停止层上形成电绝缘层并在电绝缘层上形成金属间介电层的步骤。 依次选择性地蚀刻金属间介电层和电绝缘层以限定其中露出蚀刻停止层的第一部分的开口。 该开口可以包括从沟槽的底部向下延伸的沟槽和通孔。 第一阻挡金属层形成在开口的侧壁上并且直接在蚀刻停止层的第一部分上。 从蚀刻停止层的第一部分选择性地去除第一阻挡金属层的一部分。 然后选择性地蚀刻蚀刻停止层的第一部分足够的持续时间以暴露第一金属布线图案的一部分。 在开口中形成第二金属布线图案，以便完成双镶嵌结构。

    Methods of fabricating integrated circuit memory devices having wide and narrow channel stop layers
    6.
    发明授权
    Methods of fabricating integrated circuit memory devices having wide and narrow channel stop layers 有权
    制造具有宽窄窄通道阻挡层的集成电路存储器件的方法

    公开(公告)号：US06121115A

    公开(公告)日：2000-09-19

    申请号：US135246

    申请日：1998-08-17

    申请人： Kyung-joong Joo ,  Jeong-hyuk Choi

    发明人： Kyung-joong Joo ,  Jeong-hyuk Choi

    IPC分类号： H01L21/10 ,  H01L21/76 ,  H01L21/8247 ,  H01L27/08 ,  H01L27/115 ,  H01L29/10 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11519 ,  H01L27/11521 ,  H01L29/1033

    摘要： An integrated circuit memory device includes a semiconductor substrate having a memory cell area and a select transistor area. A first field insulation layer is included in the memory cell area, and a first channel stop impurity layer is included beneath the first field insulation layer. The first channel stop impurity layer is narrower than the first field insulation area. A second field insulation layer is included in the select transistor area, and a second channel stop impurity layer is included beneath the second field insulation layer. The second channel stop impurity layer is wider than the second field insulation layer. Integrated circuit memory devices are fabricated by defining a memory cell area and a select transistor area of a semiconductor substrate. The memory cell area includes a memory cell active area and a memory cell field area. The select transistor area includes a select transistor active area and a select transistor field area. First channel stop impurity ions are implanted into the select transistor field area. A first field insulation layer is formed in the memory cell field area, and a second field insulation layer is formed in the select transistor field area, such that the first channel stop impurity ions lie beneath the second field insulation area. Second channel stop impurity ions are implanted through the central portion of the first field insulation area, such that the second channel stop impurity ions lie beneath the central portion of the first field insulation layer.

    摘要翻译： 集成电路存储器件包括具有存储单元区域和选择晶体管区域的半导体衬底。 第一场绝缘层包括在存储单元区域中，第一场绝缘层下方包括第一沟道截止杂质层。 第一通道阻挡杂质层比第一场绝缘区域窄。 第二场绝缘层包括在选择晶体管区域中，第二沟道截止杂质层包含在第二场绝缘层下面。 第二通道阻挡杂质层比第二场绝缘层宽。 通过限定半导体衬底的存储单元区域和选择晶体管区域来制造集成电路存储器件。 存储单元区域包括存储单元有效区和存储单元场区。 选择晶体管区域包括选择晶体管有源区和选择晶体管场区。 第一通道停止杂质离子注入选择晶体管场区域。 第一场绝缘层形成在存储单元场区中，第二场绝缘层形成在选择晶体管场区中，使得第一沟道阻止杂质离子位于第二场隔离区之下。 第二通道阻止杂质离子通过第一场绝缘区域的中心部分注入，使得第二通道阻止杂质离子位于第一场绝缘层的中心部分的下方。

    Semiconductor device on an opposed leadframe and method for making
    7.
    发明授权
    Semiconductor device on an opposed leadframe and method for making 失效
    相对引线框架上的半导体器件及其制造方法

    公开(公告)号：US5631192A

    公开(公告)日：1997-05-20

    申请号：US537584

    申请日：1995-10-02

    申请人： Richard E. Heppler ,  Paul L. Sullivan

    发明人： Richard E. Heppler ,  Paul L. Sullivan

    IPC分类号： H01L31/167 ,  H01L21/10

    CPC分类号： H01L31/167

    摘要： A semiconductor device (10) is formed from a single leadframe (11) by aligning two electronic components (22,24) relative to each other. The leadframe (11) has two bonding regions (30,31), which are offset from each other, and interconnect bars (13) which are used to align the two bonding regions (30,31). After the electronic components (22,24) are mounted to their respective bonding regions (30,31), the interconnect bars (13) are bent downward or upward relative to the plane formed by the leadframe (11). The bending of the interconnect bars (13) will move the two electronic components (22,24) towards each other in the direction essentially parallel to the plane of the leadframe (11). A transparent mold (28) is then formed to encapsulate the electronic components (22,24). A body (29) is then formed around the transparent mold (28) and leads (19,20). A trim and form operation releases the semiconductor device (10) from the leadframe (11).

    摘要翻译： 半导体器件（10）通过相对于彼此对准两个电子部件（22,24）由单个引线框架（11）形成。 引线框架（11）具有彼此偏移的两个接合区域（30,31）和用于对准两个接合区域（30,31）的互连条（13）。 在将电子部件（22,24）安装到其各自的接合区域（30,31）之后，互连条（13）相对于由引线框架（11）形成的平面向下或向上弯曲。 互连条（13）的弯曲将使两个电子部件（22,24）在基本上平行于引线框架（11）的平面的方向上朝彼此移动。 然后形成透明模具（28）以封装电子部件（22,24）。 然后在透明模具（28）和引线（19,20）周围形成主体（29）。 修整和成形操作从引线框架（11）释放半导体器件（10）。