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公开(公告)号：US20240311082A1
公开(公告)日：2024-09-19
申请号：US18194894
申请日：2023-04-03
发明人： Saurabh Shankar ZOND , Debojyoti Banerjee , Abhishek Ghosh , Raghavendra Shirodkar , Rakesh Dimri , Yashaswini H G
CPC分类号： G06F7/501 , H03K19/20 , H03K19/215
摘要： Provided is an apparatus that includes an integrated circuit including a static complementary metal-oxide-semiconductor based full adder (FA) circuit. The FA circuit comprises a sum generation circuit configured to generate a sum output and a carry output generation circuit configured to generate a carry output. The sum generation circuit comprises a first exclusive-NOR gate and a second exclusive-NOR gate. The carry output generation circuit comprises a first or-and-invert (OAI) gate, a second OAI gate, and a NAND gate. The first OAI gate is configured to receive an output of the NAND gate to generate one of an exclusive-NOR output or a NOR output of a first operand and a second operand. The second OAI gate is configured to receive the output of the NAND gate, an inverse of a carry input, and the generated one of the exclusive-NOR output or the NOR output to produce the carry output.
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公开(公告)号：US12088305B2
公开(公告)日：2024-09-10
申请号：US17442143
申请日：2020-03-17
发明人： Horea-Stefan Culca
IPC分类号： H03K5/153 , G01R19/165 , G01R19/175 , H03K5/1536 , H03K19/21
CPC分类号： H03K5/1536 , G01R19/16547 , G01R19/175 , H03K19/21
摘要： A circuit arrangement for monitoring an alternating voltage signal includes a comparator configured to receive the alternating voltage signal or a signal obtained from the alternating voltage signal at a first comparator input and output a comparator signal at a comparator output. The circuit arrangement further includes a zero crossing detector configured to receive a reference signal or a signal obtained from the reference signal at a monitoring input and generate a detector signal at an output of the zero crossing detector. The circuit arrangement further includes a logic circuit including a first timing element connected downstream of the zero crossing detector for generating a first clock signal and a second timing element connected downstream of the zero crossing detector for generating a second clock signal.
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公开(公告)号：US12068751B2
公开(公告)日：2024-08-20
申请号：US17852657
申请日：2022-06-29
发明人： Eric J. Stave , Tyler J. Gomm
IPC分类号： G11C11/4076 , G11C7/22 , H03K5/1534 , H03K5/156 , H03K19/21
CPC分类号： H03K5/1565 , G11C7/222 , H03K5/1534 , H03K19/21
摘要： A device includes a clock input circuit that when in operation receives a clock signal and transmits an internal clock signal based on the clock signal. The device also includes an internal clock generator coupled to the clock input circuit to receive the internal clock signal, wherein the internal clock generator comprises clock adjustment circuitry that when in operation generates a phase controlled internal clock signal having subsequent clock edges based upon a single clock edge of the internal clock signal, wherein the phase controlled internal clock signal comprises a first frequency as a multiple of a second frequency of the internal clock signal.
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公开(公告)号：US12068746B2
公开(公告)日：2024-08-20
申请号：US17773945
申请日：2020-11-02
CPC分类号： H03K19/18 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/18 , H03K19/21 , H10N52/00
摘要： A magnetic logic device having two magnetic elements and a conductive element coupled to the two magnetic elements and arranged at least substantially perpendicular to the magnetic elements, wherein the device is configured, for each magnetic element, to have a magnetisation state with a perpendicular easy axis, and to switch the magnetisation state in response to a spin current generated in the magnetic element in response to a write current applied to the magnetic element, and configured to generate, as an output, a Hall voltage across the conductive element in response to a respective read current applied to each magnetic element, wherein a magnitude of the Hall voltage is variable, depending on a direction of the magnetisation state of each magnetic element and a direction of the respective read current applied to each magnetic element, for the device to provide outputs corresponding to one of a plurality of logical operations.
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公开(公告)号：US12066487B2
公开(公告)日：2024-08-20
申请号：US17766965
申请日：2020-10-19
申请人： Robert Bosch GmbH
发明人： Andreas Schubert
IPC分类号： G01R31/317 , H03H7/06 , H03K19/21 , H03K3/037
CPC分类号： G01R31/31727 , H03H7/06 , H03K19/21 , H03K3/037
摘要： A method for simple measurement of phase shift between a first clock signal and a second clock signal is described, each clock signal having a period T0. The method includes: feeding the first clock signal into a first input of a mixer; feeding the second clock signal into a second input of the mixer; feeding the output signal of the mixer into a low pass filter; and measuring the output signal of the low pass filter, with the aid of an output voltage that is normalized to operating voltage of the mixer. A circuit for implementing the method includes a mixer and a low pass filter. The mixer includes a first input for feeding in the first clock signal, and a second input for feeding in the second clock signal. The output of the mixer is connected to the input of the low pass filter.
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公开(公告)号：US12039091B2
公开(公告)日：2024-07-16
申请号：US17496055
申请日：2021-10-07
申请人： Duke University
CPC分类号： G06F21/75 , G11C29/36 , G11C2029/3602 , H03K19/21
摘要： An integrated circuit (IC) protection circuit for an IC includes a controller with a barrier finite state machine (FSM) having a key sequence input that unlocks the controller; and a signal scrambler coupled to receive at least two initialization inputs and a primary input path and output a signal to the IC, wherein at least one initialization input of the at least two initialization inputs is based on an output of the barrier FSM. The IC protection circuit can further include a dynamic authentication circuit coupled to receive the output of the barrier finite state machine and output a signal to the signal scrambler for one of the at least two initialization inputs. The dynamic authentication circuit can be formed of a dynamic sequence generator and a dynamic sequence authenticator, each formed of one or more reconfigurable linear feedback shift registers, and a comparator.
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公开(公告)号：US12015515B2
公开(公告)日：2024-06-18
申请号：US17845860
申请日：2022-06-21
发明人： Valerio Bendotti , Nicola De Campo , Carlo Curina
IPC分类号： H04L27/36 , H03K17/687 , H03K19/096 , H03K19/21 , H04L25/40
CPC分类号： H04L27/36 , H03K17/687 , H03K19/096 , H03K19/21 , H04L25/40
摘要： A transmitter circuit receives a PWM input signal and a clock signal. A logic circuit generates a control signal as a function of the clock signal. The control signal is normally set to high, and is periodically set to low for a transmission time interval when an edge is detected in the clock signal. The transmission time interval is shorter than a half clock period of the clock signal. A tri-state transmitter receives the PWM input signal and the control signal, and produces first and a second output signals at first and second transmitter output nodes, respectively. The output signals have a voltage swing between a positive voltage and a reference voltage. An output control circuit is sensitive to the control signal and is coupled to the first and second transmitter output nodes.
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公开(公告)号：US20240195398A1
公开(公告)日：2024-06-13
申请号：US18538515
申请日：2023-12-13
申请人： LX SEMICON CO., LTD.
发明人： Jong Suk LEE , Seok Jae OH
CPC分类号： H03K5/135 , H03K3/037 , H03K17/005 , H03K19/21 , H03K2005/00286
摘要： Disclosed are a clock phase converter and a phase converting method that can generate a converted clock signal with a desired amount of delay by selecting and outputting an output signal corresponding to a preset value among output signals of a plurality of delayed clock signal generators that detect the transition of a clock signal and generate delayed clock signals by sequentially delaying the clock signal by a certain period of time.
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公开(公告)号：US20240178845A1
公开(公告)日：2024-05-30
申请号：US18514975
申请日：2023-11-20
发明人： Youngho CHOI , Donghyuk LIM , Kibaek KWON
摘要： An electronic device includes a first sample circuit configured to generate a first sampling signal by sampling an input signal in response to edges of a clock signal, a first comparator configured to generate a first logic decision signal by comparing a voltage level of the first sampling signal with a reference voltage level, an analog bang-bang phase detector configured to generate a first detection signal by executing an exclusive OR (XOR) operation on successive samples of the first logic decision signal, and a digitally controlled oscillator configured to vary a frequency of the clock signal according to the first detection signal.
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公开(公告)号：US20240178838A1
公开(公告)日：2024-05-30
申请号：US18058988
申请日：2022-11-28
发明人： Atul Kumar AGRAWAL , Abhijit Patki , Shaik BASHA
CPC分类号： H03K19/0002 , G06F3/162 , H03K5/01 , H03K19/21 , H04R3/005 , H04R3/12 , H03K2005/00013
摘要： An integrated circuit (IC) includes a tristatable output buffer having a control input. The IC includes an input buffer having a buffer output. The IC further includes a delay circuit having a delay circuit input, a first delay circuit output, and a second delay circuit output. The delay circuit input is coupled to the buffer output. The IC also includes a tristate circuit coupled to the first delay circuit output and to the second delay circuit output. The tristate circuit having a tristate circuit output coupled to the control input.
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