公开(公告)号：WO2018063404A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/055029

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： LILAK, Aaron D. ,  MA, Sean T. ,  MEHANDRU, Rishabh ,  MORROW, Patrick ,  CEA, Stephen M.

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/7846 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66 ,  H01L29/6681 ,  H01L29/785

Abstract: An integrated circuit apparatus including a body; a transistor formed on a first portion of the body, the transistor including a gate stack and a channel defined in the body between a source and a drain; and a plug formed in a second portion of the body, the plug including a material operable to impart a stress on the first portion of the body. A method of forming an integrated circuit device including forming a transistor body on a substrate; forming a transistor device in a first portion of the transistor body on a first side of the substrate; and dividing the transistor body into at least the first portion and a second portion with a plug in the transistor body, the plug including a material operable to impart a stress on the first portion of the body, wherein the material is introduced through a second side of the substrate.

Abstract translation: 包括主体的集成电路装置; 晶体管，形成在所述主体的第一部分上，所述晶体管包括栅极堆叠和限定在所述主体中的源极和漏极之间的沟道; 以及形成在本体的第二部分中的塞子，塞子包括可操作以在本体的第一部分上施加应力的材料。 一种形成集成电路器件的方法，包括：在衬底上形成晶体管主体; 在衬底的第一侧上的晶体管主体的第一部分中形成晶体管器件; 以及将晶体管主体分成至少第一部分和在晶体管主体中具有插塞的第二部分，插塞包括可操作以在主体的第一部分上施加应力的材料，其中材料通过第二侧 的基板。

公开(公告)号：WO2018063403A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/055028

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： DEWEY, Gilbert ,  METZ, Matthew V. ,  MA, Sean T. ,  HUANG, Cheng-Ying ,  GHANI, Tahir ,  MURTHY, Anand S. ,  KENNEL, Harold W. ,  MINUTILLO, Nicholas G. ,  KAVALIEROS, Jack T. ,  RACHMADY, Willy

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234

Abstract: A transistor device comprising a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel comprises a channel material that is separated from a body of the same material on a substrate. A method comprising forming a trench in a dielectric layer on an integrated circuit substrate, the trench comprising dimensions for a transistor body including a width; depositing a spacer layer in a portion of the trench, the spacer layer narrowing the width of the trench; forming a channel material in the trench through the spacer layer; recessing the dielectric layer to define a first portion of the channel material exposed and a second portion of the channel material in the trench; and separating the first portion of the channel material from the second portion of the channel material.

Abstract translation: 一种晶体管器件，包括设置在源极和漏极之间的衬底上的沟道，设置在所述沟道上的栅电极，其中所述沟道包括沟道材料，所述沟道材料与相同材料的本体分离 在衬底上。 一种方法，包括在集成电路衬底上的电介质层中形成沟槽，所述沟槽包括用于包括宽度的晶体管主体的尺寸; 在沟槽的一部分中沉积间隔层，间隔层使沟槽的宽度变窄; 穿过间隔层在沟槽中形成沟道材料; 使所述介电层凹陷以限定所述沟道材料的第一部分和所述沟道材料的第二部分; 以及将沟道材料的第一部分与沟道材料的第二部分分开。

公开(公告)号：WO2018063399A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/055020

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： THEN, Han Wui ,  DASGUPTA, Sansaptak ,  RADOSAVLJEVIC, Marko

IPC: H01L29/78 ,  H01L29/49 ,  H01L21/768

Abstract: Embodiments of the invention include a semiconductor device and methods of forming such devices. In an embodiment, the semiconductor device includes a source region, a drain region, and a channel region formed between the source region and drain region. In an embodiment, a first interlayer dielectric (ILD) may be formed over the channel region, and a first opening is formed through the first ILD. In an embodiment, a second ILD may be formed over the first ILD, and a second opening is formed through the second ILD. Embodiments of the invention include the second opening being offset from the first opening. Embodiments may also include a gate electrode formed through the first opening and the second opening. In an embodiment, the offset between the first opening and the second opening results in the formation of a field plate and a spacer that reduces a gate length of the semiconductor device.

Abstract translation: 本发明的实施例包括半导体器件和形成这种器件的方法。 在一个实施例中，半导体器件包括源极区，漏极区以及在源极区和漏极区之间形成的沟道区。 在一个实施例中，可以在沟道区上方形成第一层间电介质（ILD），并且穿过第一ILD形成第一开口。 在一个实施例中，可以在第一ILD上形成第二ILD，并且通过第二ILD形成第二开口。 本发明的实施例包括第二开口偏离第一开口。 实施例还可以包括穿过第一开口和第二开口形成的栅电极。 在一个实施例中，第一开口和第二开口之间的偏移导致形成减小半导体器件的栅极长度的场板和间隔件。

公开(公告)号：WO2018063395A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/055008

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： THEN, Han Wui ,  DASGUPTA, Sansaptak ,  RADOSAVLJEVIC, Marko

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/772

CPC classification number: H01L27/0255 ,  C23C16/042 ,  C23C16/303 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/0332 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/8258 ,  H01L27/0248 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/36 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/66136 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/861 ,  H01L29/8611

Abstract: A semiconductor structure including a group III-N semiconductor material is disposed on a silicon substrate. A group III-N transistor structure is disposed on the group III-N semiconductor material. A well is disposed in the silicon substrate. The well has a first conductivity type. A doped region is disposed in the well. The doped region has a second conductivity type that is opposite to the first conductivity type. A first electrode is connected to the well of the second conductivity type and a second electrode is connected to the doped region having a first conductivity type. The well and the doped region form a PN diode. The well or the doped region is connected to the raised drain structure of the group III-N transistor.

Abstract translation: 包括III-N族半导体材料的半导体结构设置在硅衬底上。 在III-N族半导体材料上设置III-N族晶体管结构。 在硅衬底中设置阱。 该井具有第一导电类型。 掺杂区域设置在井中。 掺杂区域具有与第一导电类型相反的第二导电类型。 第一电极连接到第二导电类型的阱，并且第二电极连接到具有第一导电类型的掺杂区域。 阱和掺杂区形成PN二极管。 阱或掺杂区域连接到III-N族晶体管的凸起漏极结构。

公开(公告)号：WO2018063322A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054760

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： LIN, Kevin L. ,  ATANASOV, Sarah E. ,  O'BRIEN, Kevin P. ,  BRISTOL, Robert L.

IPC: H01L45/00

CPC classification number: H01L45/146 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/00 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/147 ,  H01L45/1675

Abstract: Spacer-based patterning for tight-pitch and low-variability random access memory (RAM) bit cells, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate having a top layer. An array of non-volatile random access memory (RAM) bit cells is disposed on the top layer of the substrate. The array of non-volatile RAM bit cells includes columns of non-volatile RAM bit cells along a first direction and rows of non-volatile RAM bit cells along a second direction orthogonal to the first direction. A plurality of recesses is in the top layer of the substrate, along the first direction between columns of the array of non-volatile RAM bit cells.

Abstract translation: 描述了用于窄间距和低变异性随机存取存储器（RAM）位单元的基于间隔的图案化以及所产生的结构。 在一个示例中，半导体结构包括具有顶层的衬底。 非易失性随机存取存储器（RAM）位单元的阵列设置在衬底的顶层上。 非易失性RAM位单元阵列包括沿着第一方向的非易失性RAM位单元的列和沿着与第一方向正交的第二方向的非易失性RAM位单元的行。 沿着非易失性RAM位单元阵列的列之间的第一方向，衬底的顶层中有多个凹槽。

公开(公告)号：WO2018063308A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054721

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： RIOS, Rafael ,  SHARMA, Abhishek Anil ,  LE, Van H. ,  DEWEY, Gilbert William ,  KAVALIEROS, Jack T.

IPC: G11C13/00

CPC classification number: G11C13/0007 ,  G11C8/16 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/15 ,  G11C2213/56 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1666

Abstract: A two transistor, one resistor gain cell and a suitable storage element are described. In some embodiments the gain cell has a resistive memory element coupled to a common node at one end to store a value and to a source line at another end, the value being read as conductivity between the common node and the source line of the resistive memory element, a write transistor having a source coupled to a bit line, a gate coupled to a write line, and a drain coupled to the common node to write a value at the bit line to the resistive memory element upon setting the write line high, and a read transistor having a source coupled to a bit line read line and a gate coupled to the common node to read the value written to the resistive memory element as a value at the second transistor gate.

Abstract translation: 描述了两个晶体管，一个电阻器增益单元和合适的存储元件。 在一些实施例中，增益单元具有在一端耦合到公共节点的电阻存储器元件以存储值并且在另一端处存储到源极线，该值被读取为电阻存储器的公共节点和源极线之间的导电率 所述写入晶体管具有耦合到位线的源极，耦合到写入线的栅极以及耦合到所述公共节点的漏极，以在设置所述写入线为高时将所述位线处的值写入所述电阻式存储器元件， 以及读取晶体管，其具有耦合到位线读取线的源极和耦合到公共节点的栅极，以读取写入到电阻存储器元件的值作为第二晶体管栅极处的值。

公开(公告)号：WO2018063292A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054687

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： MEYERS, John G. ,  CRAFT, Leo J.

IPC: G11C5/02 ,  G11C5/06 ,  H01L23/522

CPC classification number: H01L25/18 ,  G11C5/02 ,  G11C5/06 ,  H01L23/28 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/535 ,  H01L25/0652 ,  H01L27/1052 ,  H01R12/737 ,  H05K7/1424 ,  H05K7/1447 ,  H05K7/1452 ,  H05K7/20136

Abstract: A data storage system is described that uses wafer-level packaging. In one embodiment an apparatus includes a silicon wafer, a plurality of memory cells formed directly on the wafer, an encapsulant formed over the memory cells, a plurality of wiring connections to connect the memory cells to an external interface, a memory controller, and an external interface.

Abstract translation: 描述了使用晶圆级封装的数据存储系统。 在一个实施例中，一种设备包括硅晶片，直接形成在晶片上的多个存储器单元，形成在存储器单元上方的密封剂，用于将存储器单元连接到外部接口的多个布线连接，存储器控制器和 外部接口。

公开(公告)号：WO2018063279A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054643

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： CHUAH, Tin Poay ,  LIM, Min Suet ,  TEOH, Hoay Tien ,  CHANG, Mooi Ling ,  KUAN, Chin Lee

IPC: H05K3/42 ,  H05K3/34 ,  H05K3/46

CPC classification number: H05K3/0035 ,  H05K1/184 ,  H05K3/341 ,  H05K2201/09072 ,  H05K2201/10454 ,  H05K2203/0126 ,  H05K2203/1438

Abstract: A printed circuit board (PCB) comprises a blind via and a discrete component vertically embedded within the blind via.

Abstract translation: 印刷电路板（PCB）包括盲孔和垂直嵌入盲孔内的分立元件。

公开(公告)号：WO2018063263A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054559

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： PIETAMBARAM, Srinivas V. ,  BOYAPATI, Sri Ranga Sai ,  MAY, Robert A. ,  DARMAWIKARTA, Kristof ,  SOTO GONZALEZ, Javier ,  LIM, Kwangmo

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/525

CPC classification number: H01L23/5389 ,  H01L23/00 ,  H01L24/06 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2924/18162

Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.

Abstract translation: 描述了基础层和形成导电通路的方法。 管芯焊盘形成在管芯上。 籽晶层沉积在管芯焊盘和基础层上。 在籽晶层上沉积第一光致抗蚀剂层，并且图案化第一层以形成在裸片焊盘上开口的导电线。 将导电材料沉积到导线开口中以形成导线。 在第一层上沉积第二光致抗蚀剂层，并且图案化第二层以在导电线上形成通孔开口。 将导电材料沉积到通孔开口中以形成导电通路，其中导电材料仅沉积在暴露的导电线路的部分上。 第二层和第一层被删除。 部分暴露的种子层凹陷，然后暴露导电通孔的顶部表面。

公开(公告)号：WO2018063259A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054543

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： HAFEZ, Walid M. ,  OLAC-VAW, Roman W. ,  PARK, Joodong ,  LEE, Chen-Guan ,  JAN, Chia-Hong

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417

Abstract: Metal resistors and self-aligned gate edge (SAGE) architectures having metal resistors are described. In an example, a semiconductor structure includes a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is over a first of the plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A gate edge isolation structure is laterally between and in contact with the first gate structure and the second gate structure. The gate edge isolation structure is on the trench isolation region and extends above an uppermost surface of the first gate structure and the second gate structure. A metal layer is on the gate edge isolation structure and is electrically isolated from the first gate structure and the second gate structure.

Abstract translation: 描述了具有金属电阻器的金属电阻器和自对准栅极边缘（SAGE）架构。 在一个示例中，半导体结构包括通过衬底上方的沟槽隔离区域突出的多个半导体鳍。 第一栅极结构位于多个半导体鳍中的第一个之上。 第二栅极结构位于多个半导体鳍中的第二个之上。 栅极边缘隔离结构横向地位于第一栅极结构和第二栅极结构之间并与其接触。 栅极边缘隔离结构位于沟槽隔离区域上并且延伸到第一栅极结构和第二栅极结构的最上表面之上。 金属层位于栅极边缘隔离结构上，并与第一栅极结构和第二栅极结构电隔离。