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    REGION SHIELDING WITHIN A PACKAGE OF A MICROELECTRONIC DEVICE
    96.
    发明申请
    REGION SHIELDING WITHIN A PACKAGE OF A MICROELECTRONIC DEVICE 审中-公开

    公开(公告)号：WO2022093768A1

    公开(公告)日：2022-05-05

    申请号：PCT/US2021/056581

    申请日：2021-10-26

    Applicant: INVENSAS CORPORATION

    Inventor： VARIOT, Patrick ,  SHEN, Hong

    IPC: H01L23/552 ,  H01L25/065 ,  H01L21/56

    Abstract: A microelectronic device may include a substrate, a first chip on the substrate, and a second chip on the substrate. A plurality of pillars may be located between the first chip and the second chip, wherein a first end of each pillar of the plurality of pillars is adjacent to the substrate. A spacing among the plurality of pillars is at least equal to a distance sufficient to block electromagnetic interference (EMI) and/or radio frequency interference (RFI) between the first chip and the second chip. The microelectronic device may also include a cover over at least the first chip, the second chip, and the plurality of pillars, wherein a second end of each pillar of the plurality of pillars is at least adjacent to a trench defined within the cover. The trench may include a conductive material therein.

    ACTIVE BRIDGING APPARATUS
    97.
    发明申请
    ACTIVE BRIDGING APPARATUS 审中-公开

    公开(公告)号：WO2021225730A1

    公开(公告)日：2021-11-11

    申请号：PCT/US2021/025728

    申请日：2021-04-05

    Applicant: INVENSAS CORPORATION

    Inventor： DELACRUZ, Javier A. ,  HABA, Belgacem ,  KATKAR, Rajesh

    IPC: H01L25/16 ,  H01L23/00 ,  G11C5/04 ,  G11C11/413

    Abstract: Techniques and mechanisms for coupling chiplets to microchips utilizing active bridges. The active bridges include circuits that provide various functions and capabilities that previously may have been located on the microchips and/or the chiplets. Furthermore, the active bridges may be coupled to the microchips and the chiplets via "native interconnects" utilizing direct bonding techniques. Utilizing the active bridges and the direct bonding techniques of the active bridges to the microchips and the chiplets, the pitch for the interconnects can be greatly reduced going from a pitch in the millimeters to a fine pitch that may be in a range of less than one micron to approximately five microns.

    CONNECTING MULTIPLE CHIPS USING AN INTERCONNECT DEVICE
    98.
    发明申请
    CONNECTING MULTIPLE CHIPS USING AN INTERCONNECT DEVICE 审中-公开

    公开(公告)号：WO2020257585A1

    公开(公告)日：2020-12-24

    申请号：PCT/US2020/038642

    申请日：2020-06-19

    Applicant: INVENSAS CORPORATION

    Inventor： DELACRUZ, Javier A. ,  HABA, Belgacem

    IPC: H01L23/48 ,  H01L23/00

    Abstract: Techniques are disclosed herein for connecting multiple chips using an interconnect device. In some configurations, one or more interconnect areas on a chip can be located adjacent to each other such that at least a portion of an edge of a first interconnect area is located adjacent to an edge of a second interconnect area. For example, an interconnect area can be located at a corner of a chip such that one or more edges of the interconnect area lines up with one or more edges of an interconnect area of another chip. The chip including at least one interconnect area can also be positioned and directly bonded to the interconnect device using other layouts, such as but not limited to a pinwheel layout. In some configurations more than one interconnect area can be included on a chip.

    SYMBIOTIC NETWORK ON LAYERS
    99.
    发明申请
    SYMBIOTIC NETWORK ON LAYERS 审中-公开

    公开(公告)号：WO2020247209A1

    公开(公告)日：2020-12-10

    申请号：PCT/US2020/034565

    申请日：2020-05-26

    Applicant: INVENSAS CORPORATION

    Inventor： DELACRUZ, Javier, A. ,  HABA, Belgacem ,  KATKAR, Rajesh

    IPC: G06F15/78 ,  G06F15/173 ,  H01L21/48

    Abstract: The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.

    STACKED TRANSMISSION LINE
    100.
    发明申请
    STACKED TRANSMISSION LINE 审中-公开
    堆叠传输线

    公开(公告)号：WO2017222971A1

    公开(公告)日：2017-12-28

    申请号：PCT/US2017/038107

    申请日：2017-06-19

    Applicant: INVENSAS CORPORATION

    Inventor： HUANG, Shaowu ,  DELACRUZ, Javier A. ,  HABA, Belgacem

    IPC: H01L27/02 ,  H01L27/06 ,  H01L23/498 ,  H01L23/528

    Abstract: A stacked, multi-layer transmission line is provided. The stacked transmission line includes at least a pair of conductive traces, each conductive trace having a plurality of conductive stubs electrically coupled thereto. The stubs are disposed in one or more separate spatial layers from the conductive traces.

    Abstract translation: 提供了一种堆叠的多层传输线。 堆叠的传输线包括至少一对导电迹线，每个导电迹线具有与其电耦合的多个导电短截线。 短线设置在一个或多个与导电线路分开的空间层中。

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