公开(公告)号：WO2011058718A1

公开(公告)日：2011-05-19

申请号：PCT/JP2010/006472

申请日：2010-11-02

Applicant: CANON KABUSHIKI KAISHA ,  HOSHI, Sou

Inventor： HOSHI, Sou

IPC: H01L23/498 ,  H01L23/50

CPC classification number: H01L23/50 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49844 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A semiconductor apparatus includes a multilayer interposer substrate including a power layer as an inner layer; a plurality of connection terminals provided on one surface of the interposer substrate; and a semiconductor chip mounted on the other surface of the interposer substrate. Among power terminals, ground terminals, and signal terminals provided in the semiconductor apparatus, all the power terminals are arranged in one power area and the power area includes only the power terminals.

Abstract translation: 半导体装置包括：作为内层的功率层的多层插入体基板; 设置在所述插入器基板的一个表面上的多个连接端子; 以及安装在所述插入器基板的另一表面上的半导体芯片。 在半导体装置中设置的电源端子，接地端子和信号端子中，所有电源端子配置在一个电力区域中，电力区域仅包括电力端子。

公开(公告)号：WO2010082389A1

公开(公告)日：2010-07-22

申请号：PCT/JP2009/068275

申请日：2009-10-23

Applicant: ルネサスエレクトロニクス株式会社 ,  舟山 幸太 ,  茶木原 啓 ,  石井 泰之

Inventor： 舟山　幸太 ,  茶木原　啓 ,  石井　泰之

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L23/53214 ,  H01L23/53257 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0653 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: 　選択用ｎＭＩＳ（Ｑｎｃ）の選択ゲート電極（ＣＧ）の側面に絶縁膜を介して、サイドウォール形状のメモリ用ｎＭＩＳ（Ｑｎｍ）のメモリゲート電極（ＭＧ）が自己整合により設けられたメモリセル（ＭＣ）の給電領域において、メモリゲート電極（ＭＧ）に電圧を供給するプラグ（ＰＭ）が、メモリゲート電極（ＭＧ）上に形成された層間絶縁膜（９）に形成されたコンタクトホール（ＣＭ）の内部に埋め込まれて、メモリゲート電極（ＭＧ）と電気的に接続している。選択ゲート電極（ＣＧ）の上面にはキャップ絶縁膜（ＣＡＰ）が形成されているので、プラグ（ＰＭ）と選択ゲート電極（ＣＧ）との導通を防ぐことができる。

Abstract translation: 在存储单元（MC）的馈电区域中，其中存储器nMIS（Qnm）的侧壁形状的存储栅电极（MG）通过在对准的选择栅电极（CG）的侧表面上的自对准形成 选择具有绝缘膜的nMIS（Qnc），将用于向存储栅电极（MG）施加电压的插头（PM）嵌入到形成在层间绝缘膜（9）中的接触孔（CM）中，所述接触孔 形成在存储栅电极（MG）上，与存储栅电极（MG）电连接。 由于在选择栅电极（CG）的上表面上形成帽绝缘膜（CAP），所以可以防止插头（PM）与选择栅电极（CG）之间的导电。

公开(公告)号：WO2007149580A3

公开(公告)日：2009-01-29

申请号：PCT/US2007014673

申请日：2007-06-23

Applicant: ALPHA & OMEGA SEMICONDUCTOR

Inventor： MALLIKARARJUNASWAMY SHEKAR

IPC: H01L29/76

CPC classification number: H01L29/41758 ,  H01L23/52 ,  H01L23/528 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/7816 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region disposed on opposite sides of a gate region in the semiconductor substrate. A gate electrode is formed as an electrode layer on top of the gate region for controlling an electric current transmitted between the source and the drain regions. The gate electrode layer disposed on top of the semiconductor substrate is patterned into a wave-like shaped stripes for substantially increasing an electric current conduction area between the source and drain regions across the gate.

Abstract translation: 一种半导体功率器件，其支撑在包括多个晶体管单元的半导体衬底上，每个单元具有设置在半导体衬底中的栅极区域的相对侧上的源极和漏极区域。 在栅极区域的顶部形成栅电极作为电极层，用于控制在源区和漏区之间传输的电流。 设置在半导体衬底顶部的栅极电极层被图案化成波状条纹，用于基本上增加跨越栅极的源极和漏极区域之间的电流传导区域。

公开(公告)号：WO99010929A3

公开(公告)日：1999-06-10

申请号：PCT/IB1998/001145

申请日：1998-07-27

IPC: H01L21/3205 ,  H01L21/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/52 ,  H01L23/532 ,  H01L23/535 ,  H01L51/00

CPC classification number: H01L21/486 ,  H01L21/76877 ,  H01L23/49827 ,  H01L23/49883 ,  H01L23/5328 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T29/4916 ,  H01L2924/00

Abstract: A simple and reliable method of providing a vertical interconnect between thin-film microelectronic devices is provided. In said method, a tool tip (20) is used to make a notch (104) in a vertical interconnect area (100) of two organic electrically conducting areas (3, 6) separated from each other by an organic electrically insulating area (5). The method is used in the manufacture of integrated circuits consisting substantially of organic materials.

Abstract translation: 提供了一种在薄膜微电子器件之间提供垂直互连的简单可靠的方法。 在所述方法中，工具尖端（20）用于通过有机电绝缘区域（5）彼此分离的两个有机导电区域（3,6）的垂直互连区域（100）中形成凹口（104） ）。 该方法用于制造基本上由有机材料组成的集成电路。

公开(公告)号：WO9910929A2

公开(公告)日：1999-03-04

申请号：PCT/IB9801145

申请日：1998-07-27

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PHILIPS SVENSKA AB

Inventor： DRURY CHRISTOPHER JOHN ,  MUTSAERS CORNELIS MARCUS JOHAN ,  HART CORNELIS MARIA ,  DE LEEUW DAGOBERT MICHEL

IPC: H01L21/3205 ,  H01L21/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/52 ,  H01L23/532 ,  H01L23/535 ,  H01L51/00

CPC classification number: H01L21/486 ,  H01L21/76877 ,  H01L23/49827 ,  H01L23/49883 ,  H01L23/5328 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T29/4916 ,  H01L2924/00

Abstract: A simple and reliable method of providing a vertical interconnect between thin-film microelectronic devices is provided. In said method, a tool tip (20) is used to make a notch (104) in a vertical interconnect area (100) of two organic electrically conducting areas (3, 6) separated from each other by an organic electrically insulating area (5). The method is used in the manufacture of integrated circuits consisting substantially of organic materials.

Abstract translation: 提供了一种在薄膜微电子器件之间提供垂直互连的简单且可靠的方法。 在所述方法中，使用工具尖端（20）在由有机电绝缘区域（5）彼此分离的两个有机导电区域（3,6）的垂直互连区域（100）中形成凹口（104） ）。 该方法用于制造基本上由有机材料组成的集成电路。

公开(公告)号：WO2018004680A1

公开(公告)日：2018-01-04

申请号：PCT/US2016/040804

申请日：2016-07-01

Applicant: INTEL CORPORATION

Inventor： LIAO, Szuya S. ,  GUHA, Biswajeet ,  GHANI, Tahir ,  KENYON, Christopher N. ,  GULER, Leonard P.

IPC: H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823878 ,  H01L23/535 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Self-aligned gate edge trigate and finFET devices and methods of fabricating self-aligned gate edge trigate and finFET devices are described. In an example, a semiconductor structure includes a plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation region. A gate structure is disposed over the plurality of semiconductor fins. The gate structure defines a channel region in each of the plurality of semiconductor fins. Source and drain regions are on opposing ends of the channel regions of each of the plurality of semiconductor fins, at opposing sides of the gate structure. The semiconductor structure also includes a plurality of gate edge isolation structures. Individual ones of the plurality of gate edge isolation structures alternate with individual ones of the plurality of semiconductor fins.

Abstract translation: 描述了自对准的栅极边缘触发和finFET器件以及制造自对准的栅极边缘触发器和finFET器件的方法。 在示例中，半导体结构包括设置在衬底上方并且穿过沟槽隔离区域的最上表面突出的多个半导体鳍。 栅极结构设置在多个半导体鳍上。 栅极结构限定多个半导体鳍片中的每一个中的沟道区域。 源极和漏极区位于栅极结构的相对侧的多个半导体鳍中的每一个的沟道区的相对端上。 该半导体结构还包括多个栅极边缘隔离结构。 多个栅极边缘隔离结构中的各个栅极边缘隔离结构与多个半导体鳍片中的各个半导体鳍片交替。

公开(公告)号：WO2017213734A1

公开(公告)日：2017-12-14

申请号：PCT/US2017/024801

申请日：2017-03-29

Applicant: QUALCOMM INCORPORATED

Inventor： PANT, Harshat ,  SHARIFF, Mohammed Yousuff ,  NAJDESAMII, Parissa ,  VILANGUDIPITCHAI, Ramaprasath ,  BHAN, Divjyot

IPC: H01L27/02 ,  G06F17/50 ,  H01L21/8238

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  G06F17/5072 ,  H01L21/823892 ,  H01L23/535 ,  H01L27/0886

Abstract: In an aspect of the disclosure, a MOS device for reducing routing congestion caused by using split n-well cells (704) in a merged n-well circuit block (700) is provided. The MOS device includes a first set of cells (702) adjacent to each other in a first direction. The MOS device includes a second set of cells (704) adjacent to each other in the first direction and adjacent to the first set of cells in a second direction. The second set of cells each include a first n-well (712), a second n-well (714), and a third n-well (716) separated from each other. The MOS device includes an interconnect (720) extending in the first direction in the second set of cells (704). The interconnect (720) provides a voltage source to the first n-well (712) of each of the second set of cells (704).

Abstract translation: 在本公开的一个方面中，提供了一种用于减少由于在合并的n阱电路块（700）中使用分裂的n阱单元（704）而引起的布线拥挤的MOS器件。 MOS器件包括在第一方向上彼此相邻的第一组单元（702）。 MOS器件包括在第一方向上彼此相邻且在第二方向上与第一组单元相邻的第二组单元（704）。 第二组单元各自包括彼此分离的第一n阱（712），第二n阱（714）和第三n阱（716）。 MOS器件包括在第二组单元（704）中沿第一方向延伸的互连（720）。 互连（720）向第二组电池（704）中的每一个的第一n阱（712）提供电压源。

公开(公告)号：WO2017087670A1

公开(公告)日：2017-05-26

申请号：PCT/US2016/062528

申请日：2016-11-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： ZHANG, Tong ,  ALSMEIER, Johann ,  KAI, James ,  LIU, Jin ,  ZHANG, Yanli

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/30604 ,  H01L21/76895 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/42344

Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. A source conductive line structure is provided between the substrate and the alternating stack. The source conductive line structure includes a plurality of parallel conductive rail structures extending along a same horizontal direction and adjoined to a common conductive straddling structure. Each memory stack structure straddles a vertical interface between a conductive rail structure and a support matrix. A semiconductor channel in each memory stack structure contacts a respective conductive rail structure and the support matrix.

Abstract translation: 三维存储器件包括位于衬底之上的导电层和绝缘层的交替堆叠，存储器堆叠结构的阵列。 在衬底和交替堆叠之间提供源导线结构。 源极导线结构包括沿相同水平方向延伸且邻接于共同导电跨接结构的多个平行导电轨道结构。 每个存储器堆叠结构跨越导电轨道结构和支撑矩阵之间的垂直界面。 每个存储器堆叠结构中的半导体沟道接触相应的导电轨道结构和支撑基体。

公开(公告)号：WO2017079257A1

公开(公告)日：2017-05-11

申请号：PCT/US2016/060068

申请日：2016-11-02

Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC

Inventor： PLETENETSKYY, Andriy

IPC: G02F1/1345 ,  G02F1/1362

CPC classification number: G02F1/1347 ,  G02F1/1345 ,  G02F1/13452 ,  G02F1/136277 ,  G02F2001/13478 ,  G02F2201/42 ,  G02F2202/28 ,  H01L21/486 ,  H01L23/04 ,  H01L23/053 ,  H01L23/055 ,  H01L23/057 ,  H01L23/13 ,  H01L23/32 ,  H01L23/4922 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/535 ,  H01L23/562 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: A microdisplay module (21) having a reduced size is disclosed. Conventional modules (e.g. of the LCOS type) require a large region of the package substrate (23) to accommodate and fix a flat flexible circuit connector (32) to them. The connector protrudes from the module in the same plane as the LCOS chip and the package substrate, additionally taking up significant space outside the module. In display systems with limited space there may be insufficient clearance, which can result in component failure and complicated assembly and testing. In the disclosed module, the flexible connector (32) is connected to the rear side of the package substrate (23). Electrical connection between the connector (32) and the module pads (28) on the front side are facilitated by via holes (29) passing through the substrate (23). The connector may be bent up around the edge of the package substrate to provide an improved clearance.

Abstract translation: 公开了一种尺寸减小的微型显示模块（21）。 常规模块（例如LCOS类型的）需要封装衬底（23）的较大区域来容纳并固定扁平柔性电路连接器（32）。 连接器在与LCOS芯片和封装基板相同的平面上从模块突出，另外占据模块外部的显着空间。 在空间有限的显示系统中，可能没有足够的间隙，这可能导致组件故障和复杂的组装和测试。 在所公开的模块中，柔性连接器（32）连接到封装衬底（23）的后侧。 通过穿过衬底（23）的通孔（29）促进连接器（32）和正面上的模块焊盘（28）之间的电连接。 连接器可以绕封装基板的边缘弯曲以提供改善的间隙。

公开(公告)号：WO2017058279A1

公开(公告)日：2017-04-06

申请号：PCT/US2016/015394

申请日：2016-01-28

Applicant: D3 SEMICONDUCTOR LLC

Inventor： HARRINGTON, Thomas, E.

IPC: H01L21/82 ,  H01L21/32 ,  H01L21/70 ,  H01L21/77 ,  H01L21/822

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76889 ,  H01L21/76895 ,  H01L23/53266 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7811

Abstract: A vertical drift metal-oxide-semiconductor (VDMOS) transistor with improved contact to source and body regions, and a method of fabricating the same. A masked ion implant of the source regions into opposite-type body regions defines the locations of body contact regions, which are implanted subsequently with a blanket implant. The surface of the source regions and body contact regions are silicide clad, and an overlying insulator layer deposited and planarized. Contact openings are formed through the planarized insulator layer, within which conductive plugs are formed to contact the metal silicide, and thus the source and body regions of the device. A metal conductor is formed overall to the desired thickness, and contacts the conductive plugs to provide bias to the source and body regions.

Abstract translation: 具有改善与源极和体区的接触的垂直漂移金属氧化物半导体（VDMOS）晶体管及其制造方法。 源极区域的掩模离子注入到相对体区域中限定了身体接触区域的位置，其随后用橡皮布植入物植入。 源极区域和体接触区域的表面是硅化物包层的，并且上覆的绝缘体层沉积并平坦化。 通过平坦化的绝缘体层形成接触开口，其中形成导电插塞以接触金属硅化物，从而与器件的源极和体区接触。 金属导体整体形成所需的厚度，并且与导电塞接触以向源区和身体区提供偏压。