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    LDMOS TRANSISTOR
    41.
    发明申请
    LDMOS TRANSISTOR 审中-公开
    LDMOS晶体管

    公开(公告)号：WO2009144616A1

    公开(公告)日：2009-12-03

    申请号：PCT/IB2009/052080

    申请日：2009-05-19

    Applicant: NXP B.V. ,  THEEUWEN, Stephan, J., C., H. ,  VAN RIJS, Freerk

    Inventor： THEEUWEN, Stephan, J., C., H. ,  VAN RIJS, Freerk

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L23/485 ,  H01L23/482 ,  H01L23/522 ,  H01L23/532 ,  H01L21/336 ,  H01L21/225

    CPC classification number: H01L29/7835 ,  H01L21/2257 ,  H01L21/76895 ,  H01L23/552 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/456 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An LDMOS transistor (100) on a substrate (70a, 70b) of a first conductivity type, comprises a first source region (10a), a second source region (10b) both with a source portion (73) and a common drain region (112, 212). The source portions and common drain region are of a second conductivity type opposite to the first conductivity type. The source portions and the common drain region are mutually connected through respective channel region (28a, 28b) in the substrate over which respective gate electrodes (14a, 14b) extend. The common drain region is a compound drain region comprising a first drain region (112), a second drain region (212).An isolation region (130) separating the first drain region from the second drain region by a separating distance (S) is provided in said common drain region to allow decoupling of the output capacitance and the thermal properties.

    Abstract translation: 在第一导电类型的衬底（70a，70b）上的LDMOS晶体管（100）包括第一源极区（10a），第二源极区（10b），源极部分（73）和共同漏极区域 112,212）。 源极部分和公共漏极区域是与第一导电类型相反的第二导电类型。 源极部分和公共漏极区域通过各个栅电极（14a，14b）延伸的衬底中的相应沟道区域（28a，28b）相互连接。 公共漏极区是包括第一漏极区（112），第二漏极区（212）的化合物漏极区域，将第一漏极区域与第二漏极区域分离距离（S）的隔离区域（130） 设置在所述公共漏极区域中以允许输出电容和热性质的去耦。

    STRAINED CHANNEL P-TYPE JFET AND FABRICATION METHOD THEREOF
    43.
    发明申请
    STRAINED CHANNEL P-TYPE JFET AND FABRICATION METHOD THEREOF 审中-公开
    应变通道P型JFET及其制造方法

    公开(公告)号：WO2008137724A1

    公开(公告)日：2008-11-13

    申请号：PCT/US2008/062476

    申请日：2008-05-02

    Applicant: DSM SOLUTIONS, INC. ,  SRINIVASA, Banna, R.

    Inventor： SRINIVASA, Banna, R.

    IPC: H01L29/08 ,  H01L21/337 ,  H01L29/10 ,  H01L29/165 ,  H01L29/808 ,  H01L21/225

    CPC classification number: H01L29/7843 ,  H01L21/2257 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/165 ,  H01L29/66901 ,  H01L29/7848 ,  H01L29/808

    Abstract: Enhanced hole mobility p-type JFET and fabrication methods. A p-type junction field effect transistor (200) including a substrate of n-type, a source region (204) and a drain region (206) formed in the substrate; wherein the source region and the drain region are p-type doped and at least one of the source region and the drain region is formed with silicon-germanium compound (Sil-xGex), a p-type channel (208) disposed between the source and the drain in the substrate; wherein compressive stress is induced in the p-type channel substantially along a channel length by the Sil-xGex, and an n-type gate region (210) within the p-type channel. The n-type gate region is electrically coupled to a gate contact (216) that is operable to modulate a depletion width of the p-type channel.

    Abstract translation: 增强的空穴迁移率p型JFET和制造方法。 一种p型结型场效应晶体管（200），包括形成在衬底中的n型衬底，源极区（204）和漏极区（206） 其中所述源极区和所述漏极区是p型掺杂的，并且所述源极区和所述漏极区中的至少一个由硅 - 锗化合物（Sil-xGex）形成; p型沟道（208） 和衬底中的漏极; 其中基本上沿着通过Sil-xGex的沟道长度的p型沟道和p型沟道内的n型栅极区域（210）感应压缩应力。 n型栅极区域电耦合到栅极触点（216），栅极触点可操作以调制p型沟道的耗尽宽度。

    SCALABLE PROCESS AND STRUCTURE FOR JFET FOR SMALL AND DECREASING LINE WIDTHS
    44.
    发明申请
    SCALABLE PROCESS AND STRUCTURE FOR JFET FOR SMALL AND DECREASING LINE WIDTHS 审中-公开
    用于小型和降低线宽度的JFET的可扩展过程和结构

    公开(公告)号：WO2007146872A2

    公开(公告)日：2007-12-21

    申请号：PCT/US2007070864

    申请日：2007-06-11

    Applicant: DSM SOLUTIONS INC ,  VORA MADHUKAR ,  KAPOOR ASHOK KUMAR

    Inventor： VORA MADHUKAR ,  KAPOOR ASHOK KUMAR

    IPC: H01L31/111 ,  H01L29/423 ,  H01L29/74 ,  H01L29/80

    CPC classification number: H04L7/0337 ,  H01L21/2257 ,  H01L21/76816 ,  H01L21/76897 ,  H01L29/66901 ,  H01L29/808 ,  H01L2924/0002 ,  H03L7/0812 ,  H04L7/0037 ,  H01L2924/00

    Abstract: A scalable device structure and process for forming a normally off JFET with 45 NM linewidths or less. The contacts to the source, drain and gate areas are formed by forming a layer of oxide of a thickness of less than 1000 angstroms, and, preferably 500 angstroms or less on top of the substrate. A nitride layer is formed on top of the oxide layer and holes are etched for the source, drain and gate contacts. A layer of polysilicon is then deposited so as to fill the holes and the polysilicon is polished back to planarize it flush with the nitride layer. The polysilicon contacts are then implanted with the types of impurities necessary for the channel type of the desired transistor and the impurities are driven into the semiconductor substrate below to form source, drain and gate regions.

    Abstract translation: 用于形成45 N线宽以下的常闭JFET的可扩展器件结构和工艺。 源极，漏极和栅极区域的触点通过在基板的顶部上形成厚度小于1000埃，优选为500埃或更小的氧化物层来形成。 在氧化物层的顶部形成氮化物层，蚀刻用于源极，漏极和栅极接触的孔。 然后沉积多晶硅层以填充孔，并且将多晶硅抛光回去以使其与氮化物层齐平。 然后将多晶硅触点注入所需晶体管的沟道类型所需的杂质类型，并将杂质驱动到下面的半导体衬底中以形成源极，漏极和栅极区域。

    SOURCE AND DRAIN FORMATION
    45.
    发明申请
    SOURCE AND DRAIN FORMATION 审中-公开
    源和漏区形成

    公开(公告)号：WO2007105157A2

    公开(公告)日：2007-09-20

    申请号：PCT/IB2007050789

    申请日：2007-03-09

    Applicant: NXP BV ,  SURDEANU RADU ,  AGARWAL PRABHAT

    Inventor： SURDEANU RADU ,  AGARWAL PRABHAT

    IPC: H01L21/336 ,  H01L21/225 ,  H01L21/28 ,  H01L21/84 ,  H01L29/786

    CPC classification number: H01L29/665 ,  H01L21/2257 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/78621

    Abstract: In order to form active sources and drains, a thick layer (24) of polysilicon or amorphous silicon is deposited over gate structure (10) formed on thin semiconductor layer (6) on insulating layer 4. The semiconductor layer (6) may already be lightly doped in regions (20) leaving channel region (21) under gate structure (10). An annealing step is then carried out to diffuse the dopants from the thick polysilicon or amorphous silicon layer (24) to form heavily doped source and drain regions.

    Abstract translation: 为了形成有源源极和漏极，在绝缘层4上的薄半导体层（6）上形成的栅极结构（10）上沉积多晶硅或非晶硅的厚层（24）。半导体层（6）可能已经是 在离开栅极结构（10）下方的沟道区（21）的区域（20）中轻微掺杂。 然后执行退火步骤以扩散来自厚多晶硅或非晶硅层（24）的掺杂剂以形成重掺杂源极和漏极区域。

    VERTICAL FIN-FET MOS DEVICES
    46.
    发明申请
    VERTICAL FIN-FET MOS DEVICES 审中-公开
    垂直熔池MOS器件

    公开(公告)号：WO2005079182A3

    公开(公告)日：2006-04-06

    申请号：PCT/US2004001721

    申请日：2004-01-22

    Applicant: IBM ,  BEINTNER JOCHEN ,  CHIDAMBARRAO DURESETI ,  DIVKARUNI RAMACHANDRA

    Inventor： BEINTNER JOCHEN ,  CHIDAMBARRAO DURESETI ,  DIVKARUNI RAMACHANDRA

    IPC: H01L29/786 ,  H01L21/336 ,  H01L21/8238

    CPC classification number: H01L29/78642 ,  H01L21/2257 ,  H01L29/66787

    Abstract: A new class of high-density, vertical Fin-FET devices that exhibit low contact resistance is described. These vertical Fin-FET devices have vertical silicon "fins" (12A) that act as the transistor body. Doped source and drain regions (26A, 28A) are formed at the bottoms and tops, respectively, of the fins (12A). Gates (24A, 24B) are formed along sidewalls of the fins. Current flows vertically through the fins (12A) between the source and drain regions (26A, 28A) when an appropriate bias is applied to the gates (24A, 24B). An integrated process for forming pFET, nFET, multi-fin, single-fin, multi-gate and double-gate vertical Fin-FETs simultaneously is described.

    Abstract translation: 描述了一种新型的具有低接触电阻的高密度垂直Fin-FET器件。 这些垂直Fin-FET器件具有用作晶体管体的垂直硅“鳍”（12A）。 掺杂的源极和漏极区域（26A，28A）分别形成在鳍片（12A）的底部和顶部。 盖板（24A，24B）沿翅片的侧壁形成。 当适当的偏压被施加到栅极（24A，24B）时，电流垂直地流过源极和漏极区域（26A，28A）之间的鳍片（12A）。 描述了同时形成pFET，nFET，多鳍，单鳍，多栅极和双栅极垂直鳍FET的集成工艺。

    VERTICAL FIN-FET MOS DEVICES
    47.
    发明申请
    VERTICAL FIN-FET MOS DEVICES 审中-公开
    垂直熔池MOS器件

    公开(公告)号：WO2005079182A2

    公开(公告)日：2005-09-01

    申请号：PCT/US2004/001721

    申请日：2004-01-22

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BEINTNER, Jochen ,  CHIDAMBARRAO, Dureseti ,  DIVKARUNI, Ramachandra

    Inventor： BEINTNER, Jochen ,  CHIDAMBARRAO, Dureseti ,  DIVKARUNI, Ramachandra

    CPC classification number: H01L29/78642 ,  H01L21/2257 ,  H01L29/66787

    Abstract: A new class of high-density, vertical Fin-FET devices that exhibit low contact resistance is described. These vertical Fin-FET devices have vertical silicon “fins” (12A) that act as the transistor body. Doped source and drain regions (26A, 28A) are formed at the bottoms and tops, respectively, of the fins (12A). Gates (24A, 24B) are formed along sidewalls of the fins. Current flows vertically through the fins (12A) between the source and drain regions (26A, 28A) when an appropriate bias is applied to the gates (24A, 24B). An integrated process for forming pFET, nFET, multi-fin, single-fin, multi-gate and double-gate vertical Fin-FETs simultaneously is described.

    Abstract translation: 描述了一种新型的具有低接触电阻的高密度垂直Fin-FET器件。 这些垂直Fin-FET器件具有用作晶体管体的垂直硅“鳍”（12A）。 掺杂的源极和漏极区域（26A，28A）分别形成在鳍片（12A）的底部和顶部。 盖板（24A，24B）沿翅片的侧壁形成。 当适当的偏压被施加到栅极（24A，24B）时，电流垂直地流过源极和漏极区域（26A，28A）之间的鳍片（12A）。 描述了同时形成pFET，nFET，多鳍，单鳍，多栅极和双栅极垂直鳍FET的集成工艺。

    HIGH VOLTAGE POWER MOSFET HAVING A VOLTAGE SUSTAINING REGION AND DIFFUSION FROM REGIONS OF OPPOSITELY DOPED POLYSILICON
    48.
    发明申请
    HIGH VOLTAGE POWER MOSFET HAVING A VOLTAGE SUSTAINING REGION AND DIFFUSION FROM REGIONS OF OPPOSITELY DOPED POLYSILICON 审中-公开
    具有电压持续区域的高压功率MOSFET和来自不同掺杂多晶硅的区域的扩散

    公开(公告)号：WO03058684A3

    公开(公告)日：2003-10-02

    申请号：PCT/US0241809

    申请日：2002-12-30

    Applicant: GEN SEMICONDUCTOR INC

    Inventor： BLANCHARD RICHARD A

    IPC: H01L21/331 ,  H01L21/22 ,  H01L21/225 ,  H01L21/329 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78 ,  H01L29/76 ,  H01L21/66

    CPC classification number: H01L29/7802 ,  H01L21/2257 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395

    Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first (2) or second conductivity (1) type and then forming a voltage sustaining region on the substrate (1). The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate (1) and forming at least one trench (520) in the epitaxial layer. A first layer of polysilicon (512) having a second dopant of the second conductivity type is deposited in the trench (520). The second dopant is diffused to form a doped epitaxial region adjacent to the trench (520) and in the epitaxial layer. A second layer of polysilicon (510) having a first dopant of the first conductivity type is subsequently deposited in the trench (520). The first and second dopants respectively located in the second and first layers of polysilicon (512) are interdiffused to achieve electrical compensation in the first and second layers of polysilicon (512). Finally, at least one region of the second conductivity type is formed over the voltage sustaining region to define a junction therebetween.

    Abstract translation: 提供了形成功率半导体器件的方法。 该方法开始于提供第一（2）或第二导电（1）类型的衬底，然后在衬底（1）上形成电压维持区域。 通过在衬底（1）上沉积第一导电类型的外延层并在外延层中形成至少一个沟槽（520）形成电压维持区。 具有第二导电类型的第二掺杂剂的第一多晶硅层（512）沉积在沟槽520中。 第二掺杂剂被扩散以形成邻近沟槽（520）和外延层中的掺杂外延区域。 具有第一导电类型的第一掺杂剂的第二多晶硅层（510）随后沉积在沟槽520中。 分别位于第二和第一多晶硅层（512）中的第一和第二掺杂剂是相互扩散的，以在多晶硅的第一和第二层（512）中实现电补偿。 最后，在电压维持区域上形成第二导电类型的至少一个区域以限定它们之间的接合。

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