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    A TECHNIQUE FOR FORMINIG AN INTERLAYER DIELECTRIC MATERIAL OF INCREASED RELIABILITY ABOVE A STRUCTURE INCLUDING CLOSELY SPACED LINES
    4.
    发明申请
    A TECHNIQUE FOR FORMINIG AN INTERLAYER DIELECTRIC MATERIAL OF INCREASED RELIABILITY ABOVE A STRUCTURE INCLUDING CLOSELY SPACED LINES 审中-公开
    用于形成中间层介电材料的技术在上述结构之间增加可靠性，包括闭合间距线

    公开(公告)号：WO2009005788A2

    公开(公告)日：2009-01-08

    申请号：PCT/US2008008153

    申请日：2008-06-30

    Applicant: ADVANCED MICRO DEVICES INC ,  FEUSTEL FRANK ,  FROHBERG KAI ,  PETERS CARSTEN

    Inventor： FEUSTEL FRANK ,  FROHBERG KAI ,  PETERS CARSTEN

    IPC: H01L21/768

    CPC classification number: H01L21/76832 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L29/7843

    Abstract: By removing excess material of an interlayer dielectric material (207, 307) deposited by SACVD, the gap filling capabilities of this deposition technique may be exploited, while, on the other hand, negative effects of this material may be reduced. In other aspects, a buffer material (360), such as silicon dioxide, may be formed prior to depositing the interlayer dielectric material (207, 307) on the basis of SACVD, thereby creating enhanced uniformity during the deposition process when depositing the interlayer dielectric material (207, 307) on dielectric layers having different high intrinsic stress levels. Consequently, the reliability of the interlayer dielectric material (207, 307) may be enhanced while nevertheless maintaining the advantages provided by an SACVD deposition.

    Abstract translation: 通过除去通过SACVD沉积的层间电介质材料（207,307）的多余材料，可以利用该沉积技术的间隙填充能力，而另一方面可减少该材料的负面影响。 在其它方面，可以在基于SACVD沉积层间绝缘材料（207,307）之前形成诸如二氧化硅的缓冲材料（360），从而在沉积过程中产生增强的均匀性，当沉积层间电介质 材料（207,307）在具有不同高固有应力水平的电介质层上。 因此，可以提高层间绝缘材料（207,307）的可靠性，同时保持由SACVD沉积提供的优点。

    LOCAL SILICIDATION OF VIA BOTTOMS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES
    6.
    发明申请
    LOCAL SILICIDATION OF VIA BOTTOMS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES 审中-公开
    在半导体器件金属化系统中通过底部的局部硅化

    公开(公告)号：WO2010078074A1

    公开(公告)日：2010-07-08

    申请号：PCT/US2009/068673

    申请日：2009-12-18

    Applicant: GLOBALFOUNDRIES INC. ,  LETZ, Tobias ,  FEUSTEL, Frank

    Inventor： LETZ, Tobias ,  FEUSTEL, Frank

    IPC: H01L21/768

    CPC classification number: H01L21/76814 ,  H01L21/76826 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76886

    Abstract: Electromigration behavior in complex metallization systems of semiconductor devices may be enhanced at critical areas between a metal line and a via by locally forming a copper/silicon compound. In some illustrative embodiments, the formation of the copper/ silicon compound may be combined with other treatments for cleaning the exposed surface areas and/or modifying the molecular structure thereof.

    Abstract translation: 通过局部形成铜/硅化合物，可以在金属线和通孔之间的关键区域增强半导体器件复杂金属化系统中的电迁移行为。 在一些说明性实施例中，铜/硅化合物的形成可以与用于清洁暴露的表面区域和/或改变其分子结构的其它处理组合。

    USING A CAP LAYER IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES AS A CMP AND ETCH STOP LAYER
    8.
    发明申请
    USING A CAP LAYER IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES AS A CMP AND ETCH STOP LAYER 审中-公开
    在作为CMP和蚀刻停止层的半导体器件的金属化系统中使用CAP层

    公开(公告)号：WO2010022969A1

    公开(公告)日：2010-03-04

    申请号：PCT/EP2009/006257

    申请日：2009-08-28

    Applicant: ADVANCED MICRO DEVICES, INC. ,  WERNER, Thomas ,  FROHBERG, Kai ,  FEUSTEL, Frank

    Inventor： WERNER, Thomas ,  FROHBERG, Kai ,  FEUSTEL, Frank

    IPC: H01L21/321 ,  H01L21/768

    CPC classification number: H01L21/7684 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/76829 ,  H01L21/76832

    Abstract: During the manufacturing of advanced metallization systems, a dielectric cap layer formed on a sensitive dielectric material may be partially maintained during a CMP process for removing excess metal, thereby avoiding the necessity for depositing a dedicated etch stop material, as may be required in conventional approaches when substantially completely consuming the dielectric cap material during the CMP process. Hence, reduced process complexity and/or enhanced flexibility may be accomplished in combination with increased integrity of the low-k dielectric material.

    Abstract translation: 在高级金属化系统的制造过程中，在CMP工艺中可以部分地保持形成在敏感电介质材料上的电介质盖层，以去除多余的金属，从而避免沉积专用蚀刻停止材料的必要性，如常规方法中所需要的 当在CMP工艺期间基本上完全消耗电介质盖材料时。 因此，降低的工艺复杂性和/或增强的柔性可以与低k介电材料的增加的完整性相结合来实现。

    A NANO IMPRINT TECHNIQUE WITH INCREASED FLEXIBILITY WITH RESPECT TO ALIGNMENT AND FEATURE SHAPING
    9.
    发明申请
    A NANO IMPRINT TECHNIQUE WITH INCREASED FLEXIBILITY WITH RESPECT TO ALIGNMENT AND FEATURE SHAPING 审中-公开
    与对准和特征形状相比具有增强灵活性的纳米印刷技术

    公开(公告)号：WO2008005087A2

    公开(公告)日：2008-01-10

    申请号：PCT/US2007008371

    申请日：2007-04-05

    Applicant: ADVANCED MICRO DEVICES INC ,  SEIDEL ROBERT ,  PETERS CARSTEN ,  FEUSTEL FRANK

    Inventor： SEIDEL ROBERT ,  PETERS CARSTEN ,  FEUSTEL FRANK

    IPC: H01L21/768

    CPC classification number: H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76817 ,  H01L2221/1021

    Abstract: By forming metallization structures on the basis of an imprint technique, in which via openings and trenches may be commonly formed, a significant reduction of process complexity may be achieved due to the omission of at least one further alignment process as required in conventional process techniques. Furthermore, the flexibility and efficiency of imprint lithography may be increased by providing appropriately designed imprint molds in order to provide via openings and trenches exhibiting an increased fill capability, thereby also improving the performance of the finally obtained metallization structures with respect to reliability, resistance against electromigration and the like.

    Abstract translation: 通过基于通常形成通孔和沟槽的压印技术形成金属化结构，由于在常规工艺技术中根据需要省略了至少一个进一步的对准过程，可以实现工艺复杂性的显着降低。 此外，可以通过提供适当设计的压印模具来提高压印光刻的灵活性和效率，以便提供表现出增加的填充能力的通孔开口和沟槽，从而也提高了最终获得的金属化结构在可靠性，抗性 电迁移等。

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