Abstract:
A microelectronic assembly (210) includes a substrate (212) having a first surface (214) and a second surface (216) remote from the first surface (214). A microelectronic element (222) overlies the first surface (214) and first electrically conductive elements (228) are exposed at one of the first surface (214) and the second surface (222). Some of the first conductive elements (228) are electrically connected to the microelectronic element (222). Wire bonds (232) have bases (234) joined to the conductive elements (228) and end surfaces (238) remote from the substrate (212) and the bases (234), each wire bond (232) defining an edge surface (237) extending between the base (234) and the end surface (238). An encapsulation layer (242) extends from the first surface (214) and fills spaces between the wire bonds (232) such that the wire bonds (232) are separated by the encapsulation layer (242). Unencapsulated portions of the wire bonds (232) are defined by at least portions of the end surfaces (238) of the wire bonds that are uncovered by the encapsulation layer (242).
Abstract:
A method of making a microelectronic assembly includes providing a microelectronic package having a substrate 400, a microelectronic element 410 overlying the substrate 400 and at least two conductive elements 418 projecting from a surface 402 of the substrate 400, the at least two conductive elements 418 having surfaces 434 remote from the surface 402 of the substrate 400. The method includes compressing the at least two conductive elements 418 so that the remote surfaces 434 thereof lie in a common plane, and after the compressing step, providing an encapsulant material 430 around the at least two conductive elements 418 for supporting the microelectronic package and so that the remote surfaces 434 of the at least two conductive elements 418 remain accessible at an exterior surface of the encapsulant material 430.
Abstract:
A method of making a microelectronic assembly includes providing a microelectronic package having a substrate 400, a microelectronic element 410 overlying the substrate 400 and at least two conductive elements 418 projecting from a surface 402 of the substrate 400, the at least two conductive elements 418 having surfaces 434 remote from the surface 402 of the substrate 400. The method includes compressing the at least two conductive elements 418 so that the remote surfaces 434 thereof lie in a common plane, and after the compressing step, providing an encapsulant material 430 around the at least two conductive elements 418 for supporting the microelectronic package and so that the remote surfaces 434 of the at least two conductive elements 418 remain accessible at an exterior surface of the encapsulant material 430.
Abstract:
A method for making a microelectronic assembly includes providing a microelectronic element 30 with first conductive elements and a dielectric element 50 with second conductive elements. At least some of either the first conductive elements or the second conductive elements may be conductive posts 40 and other of the first or second conductive elements may include a bond metal 10 disposed between some of the conductive posts 40. An underfill layer 60 may overly some of the first or second conductive elements. At least one of the first conductive elements may be moved towards the other of the second conductive elements so that the posts pierce the underfill layer 60 and at least deform the bond metal 10. The microelectronic element 30 and the dielectric element 50 can be heated to join them together. The height of the posts 40 above the surface may be at least forty percent of a distance between surfaces of the microelectronic element 30 and dielectric element 50.
Abstract:
A microelectronic package includes a lower unit 11 OA having a lower unit substrate with conductive features and a top and bottom surface 64, 66. The lower unit IIOA includes., one or more lower unit chips 112A, 132A overlying the top surface 64 of the' lower unit substrate 62 that are electrically connected to the conductive features 68, 70 of the lower unit substrate 62. The microelectronic package also includes an upper unit 110 including an upper unit substrate having conductive features, top and bottom surfaces and a hole extending between such top and bottom surfaces. The upper unit further includes one or more upper unit chips 112, 132 overlying the top surface of the upper unit substrate and electrically connected to the conductive features of the upper unit substrate by connections extending within the hole 76.
Abstract:
A method for making a microelectronic assembly includes providing a microelectronic element 30 with first conductive elements and a dielectric element 50 with second conductive elements. At least some of either the first conductive elements or the second conductive elements may be conductive posts 40 and other of the first or second conductive elements may include a bond metal 10 disposed between some of the conductive posts 40. An underfill layer 60 may overly some of the first or second conductive elements. At least one of the first conductive elements may be moved towards the other of the second conductive elements so that the posts pierce the underfill layer 60 and at least deform the bond metal 10. The microelectronic element 30 and the dielectric element 50 can be heated to join them together. The height of the posts 40 above the surface may be at least forty percent of a distance between surfaces of the microelectronic element 30 and dielectric element 50.
Abstract:
A microelectronic package includes a lower unit 110A having a lower unit substrate with conductive features and a top and bottom surface 64, 66. The lower unit 110A includes., one or more lower unit chips 112A, 132A overlying the top surface 64 of the lower unit substrate 62 that are electrically connected to the conductive features 68 of the lower unit substrate 62. The microelectronic package also includes an upper unit 110 including an upper unit substrate having conductive features, top and bottom surfaces and a hole extending between such top and bottom surfaces. The upper unit further includes one or more upper unit chips 112, 132 overlying the top surface of the upper unit substrate and electrically connected to the conductive features 141 of the upper unit substrate by connections extending within the hole 76.