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公开(公告)号：WO2016083332A1
公开(公告)日：2016-06-02
申请号：PCT/EP2015/077424
申请日：2015-11-24
Applicant: IMEC VZW
Inventor： KIM, Soon-Wook , PENG, Lan , VERDONCK, Patrick , MILLER, Robert , BEYER, Gerald , BEYNE, Eric
CPC classification number: H01L24/83 , H01L21/02065 , H01L21/02164 , H01L21/02167 , H01L21/02211 , H01L21/02274 , H01L21/31053 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/32 , H01L24/80 , H01L25/0657 , H01L2224/03452 , H01L2224/03462 , H01L2224/03616 , H01L2224/03845 , H01L2224/03848 , H01L2224/05568 , H01L2224/05573 , H01L2224/05576 , H01L2224/05686 , H01L2224/08121 , H01L2224/08145 , H01L2224/32501 , H01L2224/80097 , H01L2224/80201 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/80948 , H01L2224/83031 , H01L2224/83047 , H01L2224/83048 , H01L2224/83359 , H01L2924/00012 , H01L2924/0504 , H01L2924/00014 , H01L2924/20106 , H01L2924/2011
Abstract: A method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding is described. The substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. Then a layer of SiCN is deposited onto the dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of 1 tenth of a nanometre. Then the substrates are subjected to a pre-bond annealing step and then bonded by direct bonding, possibly preceded by one or more pre- treatments of the contact surfaces, and followed by a post- bond annealing step, at a temperature of less than or equal to 250°C. It has been found that the bond strength is excellent, even at the above named annealing temperatures, which are lower than presently known in the art.
Abstract translation: 描述通过直接接合将第一半导体衬底接合到第二半导体衬底的方法。 这些基板都在其接触表面上设置有电介质层，接着是用于减小电介质层粗糙度的CMP步骤。 然后将一层SiCN沉积到介电层上，随后是CMP步骤，其将SiCN层的粗糙度降低到十分之一纳米。 然后将基板进行预结合退火步骤，然后通过直接接合进行粘合，可能之前是接触表面的一个或多个预处理，然后是后接合退火步骤，其温度低于或等于 等于250°C。 已经发现，即使在上述命名的退火温度下，粘合强度也是优异的，其比现有技术中已知的低。
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公开(公告)号：WO2015054413A1
公开(公告)日：2015-04-16
申请号：PCT/US2014/059737
申请日：2014-10-08
Applicant: INVENSAS CORPORATION
Inventor： UZOH, Cyprian, Emeka , KATKAR, Rajesh
IPC: H01L23/498 , H01L21/48
CPC classification number: H01L24/11 , H01L21/3213 , H01L21/32139 , H01L21/4853 , H01L21/76885 , H01L23/49811 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/02166 , H01L2224/03462 , H01L2224/0348 , H01L2224/0362 , H01L2224/03823 , H01L2224/0401 , H01L2224/05023 , H01L2224/05082 , H01L2224/05147 , H01L2224/05164 , H01L2224/05554 , H01L2224/05556 , H01L2224/05558 , H01L2224/05564 , H01L2224/05565 , H01L2224/05568 , H01L2224/05578 , H01L2224/05582 , H01L2224/05611 , H01L2224/05664 , H01L2224/05686 , H01L2224/0569 , H01L2224/10126 , H01L2224/10145 , H01L2224/11013 , H01L2224/1111 , H01L2224/11462 , H01L2224/11464 , H01L2224/1182 , H01L2224/11849 , H01L2224/131 , H01L2224/81815 , H01L2924/15787 , H01L2924/15788 , H01L2924/014 , H01L2924/00012 , H01L2924/00014 , H01L2924/01029 , H01L2924/00
Abstract: An apparatus relating generally to a substrate is disclosed. In this apparatus, a first metal layer is on the substrate. The first metal layer has an opening. The opening of the first metal layer has a bottom and one or more sides extending from the bottom. A second metal layer is on the first metal layer. The first metal layer and the second metal layer provide a bowl-shaped structure. An inner surface of the bowl-shaped structure is defined responsive to the opening of the first metal layer and the second metal layer thereon. The opening of the bowl-shaped structure is configured to receive and at least partially retain a bonding material during a reflow process.
Abstract translation: 公开了一般涉及基板的装置。 在该装置中，第一金属层位于基板上。 第一金属层具有开口。 第一金属层的开口具有从底部延伸的底部和一个或多个侧面。 第二金属层位于第一金属层上。 第一金属层和第二金属层提供碗形结构。 碗形结构的内表面是响应于其上的第一金属层和第二金属层的开口而定义的。 碗形结构的开口构造成在回流过程期间接收并且至少部分地保持接合材料。
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公开(公告)号：WO2017105524A1
公开(公告)日：2017-06-22
申请号：PCT/US2015/068082
申请日：2015-12-30
Applicant: GOOGLE INC. , MUTUS, Joshua Yousouf , LUCERO, Erik Anthony
Inventor： MUTUS, Joshua Yousouf , LUCERO, Erik Anthony
IPC: H01L27/18 , H01L23/498
CPC classification number: H01L27/18 , H01L23/49816 , H01L23/49888 , H01L24/05 , H01L24/10 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0345 , H01L2224/0362 , H01L2224/0384 , H01L2224/0401 , H01L2224/05023 , H01L2224/05124 , H01L2224/05179 , H01L2224/05186 , H01L2224/05564 , H01L2224/05568 , H01L2224/05669 , H01L2224/05684 , H01L2224/05686 , H01L2224/1145 , H01L2224/13023 , H01L2224/13109 , H01L2224/13116 , H01L2224/13164 , H01L2224/13179 , H01L2224/13183 , H01L2224/16145 , H01L2224/81013 , H01L2224/81193 , H01L2224/81201 , H01L2224/81409 , H01L2225/06513 , H01L2225/06541 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/00014 , H01L2924/04941
Abstract: A device (100) includes a first chip (104) having a first circuit element (112), a first interconnect pad (116) in electrical contact (118) with the first circuit element, and a barrier layer (120) on the first interconnect pad, a superconducting bump bond (106) on the barrier layer, and a second chip (102) joined to the first chip by the superconducting bump bond, the second chip having a quantum circuit element (108), in which the superconducting bump bond provides an electrical connection between the first circuit element and the quantum circuit element.
Abstract translation: 设备（100）包括具有第一电路元件（112）的第一芯片（104），与第一电路元件电接触（118）的第一互连焊盘（116），以及 所述第一互连焊盘上的阻挡层（120），所述阻挡层上的超导凸点结合（106）以及通过所述超导凸点结合与所述第一芯片结合的第二芯片（102），所述第二芯片具有量子电路元件 其中超导凸块接合提供第一电路元件和量子电路元件之间的电连接。
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公开(公告)号：WO2017021231A1
公开(公告)日：2017-02-09
申请号：PCT/EP2016/067827
申请日：2016-07-26
Inventor： FOURNEL, Frank , BAILLIN, Xavier , CHERAMY, Séverine , LEDUC, Patrick , SANCHEZ, Loic
IPC: H01L21/60
CPC classification number: H01L24/80 , H01L24/03 , H01L24/05 , H01L24/97 , H01L2224/0381 , H01L2224/05568 , H01L2224/056 , H01L2224/05686 , H01L2224/08148 , H01L2224/08238 , H01L2224/80004 , H01L2224/80013 , H01L2224/80143 , H01L2224/80205 , H01L2224/80894 , H01L2224/80948 , H01L2224/95146 , H01L2224/97 , H01L2924/00014 , H01L2924/05442
Abstract: Procédé de collage direct d'une puce électronique (100) sur un substrat (102) ou sur une autre puce électronique, comportant les étapes de : - traitement hydrophile d'une partie (105) d'une face de la puce électronique et d'une partie (110) d'une face (108) du substrat ou de l'autre puce électronique; - dépôt d'un fluide aqueux (112) sur la partie de la face du substrat ou de la deuxième puce électronique; - dépôt de la partie de la face de la puce électronique sur le fluide aqueux; - séchage du fluide aqueux jusqu'à une solidarisation de la partie de la face de la puce électronique avec la partie de la face du substrat ou de l'autre puce électronique; et comportant en outre, pendant au moins une partie du séchage du fluide aqueux, une émission d'ultrasons dans le fluide aqueux à travers le substrat ou l'autre puce électronique.
Abstract translation: 本发明涉及一种用于将电子芯片（100）直接接合到基板（102）或另一电子芯片上的方法，所述方法包括以下步骤：对表面的一部分（105）进行亲水处理 所述电子芯片和所述基板或所述另一个电子芯片的表面（108）的一部分（110） 将水性流体（112）沉积在所述基底或所述第二电子芯片的所述表面的所述部分上; 将所述电子芯片的所述表面的所述部分沉积在所述水性流体上; 干燥含水流体直到电子芯片的表面部分刚性地连接到基板或另一个电子芯片表面的部分; 所述方法还在水性流体的至少部分干燥过程中还包括通过基底或其它电子芯片将超声发射到水性流体中。
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公开(公告)号：WO2012067992A3
公开(公告)日：2012-12-20
申请号：PCT/US2011060553
申请日：2011-11-14
Applicant: TESSERA INC , HABA BELGACEM
Inventor： HABA BELGACEM
IPC: H01L23/485 , H01L21/60
CPC classification number: H01L24/05 , H01L23/49838 , H01L24/03 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L25/0657 , H01L2224/03001 , H01L2224/03003 , H01L2224/0311 , H01L2224/0401 , H01L2224/04026 , H01L2224/05551 , H01L2224/05552 , H01L2224/05555 , H01L2224/05568 , H01L2224/0557 , H01L2224/05571 , H01L2224/05572 , H01L2224/05576 , H01L2224/05644 , H01L2224/05655 , H01L2224/05686 , H01L2224/0569 , H01L2224/13022 , H01L2224/13023 , H01L2224/16145 , H01L2224/16221 , H01L2224/29018 , H01L2224/29026 , H01L2224/32145 , H01L2224/32225 , H01L2225/06513 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1032 , H01L2924/10329 , H01L2924/1037 , H01L2924/1203 , H01L2924/12042 , H01L2924/1304 , H01L2924/14 , H01L2924/1433 , H01L2924/1436 , H01L2924/1437 , H01L2924/1461 , H01L2924/20107 , H01L2924/00014 , H01L2924/00
Abstract: An assembly 100 and method of making same are provided. The assembly 100 can include a first component 105 including a dielectric region 120 having an exposed surface 122, a conductive pad 134 at the surface 122 defined by a conductive element 132 having at least a portion extending in an oscillating or spiral path along the surface 122, and a an electrically conductive bonding material 140 joined to the conductive pad 134 and bridging an exposed portion 137 of the dielectric surface 122 between adjacent segments 136, 138. The conductive pad 134 can permit electrical interconnection of the first component 105 with a second component 107 having a terminal 108 joined to the pad 134 through the electrically conductive bonding material 140. The path of the conductive element 132 may or may not overlap or cross itself.
Abstract translation: 提供组件100及其制造方法。 组件100可以包括第一部件105，其包括具有暴露表面122的电介质区域120，在由导电元件132限定的表面122处的导电焊盘134，导电元件132具有沿着表面122的振荡或螺旋路径延伸的至少一部分 以及连接到导电焊盘134并桥接相邻段136,138之间的电介质表面122的暴露部分137的导电接合材料140.导电焊盘134可以允许第一部件105与第二部件 107具有通过导电接合材料140接合到焊盘134的端子108.导电元件132的路径可以或可以不与其自身重叠或交叉。
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Patent Agency Ranking
公开(公告)号：WO2015040784A1
公开(公告)日：2015-03-26
申请号：PCT/JP2014/004197
申请日：2014-08-18
Applicant: パナソニックIPマネジメント株式会社
IPC: H01L25/065 , H01L21/3205 , H01L21/768 , H01L23/522 , H01L23/532 , H01L25/07 , H01L25/18
CPC classification number: H01L25/0657 , H01L23/34 , H01L23/481 , H01L23/522 , H01L23/53214 , H01L23/53228 , H01L23/53257 , H01L24/05 , H01L24/08 , H01L24/09 , H01L24/80 , H01L25/065 , H01L25/07 , H01L25/18 , H01L2224/05025 , H01L2224/05557 , H01L2224/05571 , H01L2224/05576 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/05684 , H01L2224/05686 , H01L2224/08057 , H01L2224/08145 , H01L2224/08146 , H01L2224/08147 , H01L2224/80895 , H01L2224/80896 , H01L2225/06541 , H01L2924/00014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05442
Abstract: 半導体装置は、半導体基板の主面上に順次形成され、機能素子と、配線層と、接合電極を含む接続層とを有する第１積層体と、半導体基板の主面上に順次形成され、機能素子と、配線層と、接合電極を含む接続層とを有する第２積層体とを備えている。第１積層体と第２積層体とは、接合電極と接合電極とが互いに対向して直接接合することにより接合されており、第１積層体と第２積層体との接合界面の一部には、空間部が形成されている。
Abstract translation: 一种半导体装置，具备：具有功能元件的第一层叠体，布线层和包括接合电极的连接层，所述第一层叠体依次形成在半导体衬底的主表面上; 以及具有功能元件，布线层和包括接合电极的连接层的第二层压制品，所述第二层叠制品依次形成在所述半导体衬底的主表面上。 第一层叠体和第二层叠体通过彼此直接接合的接合电极而相互连接，并且在第一层叠体与第二层叠体的接合界面的一部分形成空间部 文章。
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公开(公告)号：WO2014042811A1
公开(公告)日：2014-03-20
申请号：PCT/US2013/055032
申请日：2013-08-15
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： DAUBENSPECK, Timothy, H. , GAMBINO, Jeffrey, P. , MUZZY, Christopher, D. , SAUTER, Wolfgang , SULLIVAN, Timothy, D.
IPC: H01L21/44 , H01L21/60 , H01L21/768
CPC classification number: H01L21/563 , H01L23/3121 , H01L23/3142 , H01L23/3192 , H01L23/49811 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/32 , H01L24/73 , H01L2224/024 , H01L2224/0401 , H01L2224/05023 , H01L2224/05024 , H01L2224/05082 , H01L2224/05113 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05613 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/11912 , H01L2224/13023 , H01L2224/13076 , H01L2224/13078 , H01L2224/13082 , H01L2224/131 , H01L2224/13113 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13181 , H01L2224/13184 , H01L2224/13186 , H01L2224/73104 , H01L2224/73204 , H01L2924/0132 , H01L2924/04941 , H01L2924/04953 , H01L2924/07025 , H01L2924/14 , H01L2924/00014 , H01L2924/01074 , H01L2924/014
Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, a method can include: providing a precursor interconnect structure having: a photosensitive polyimide (PSPI) layer (4); a controlled collapse chip connection (C4) bump (10) overlying the PSPI layer; and a solder (18) overlying the C4 bump and contacting a side (20) of the C4 bump. The method can further include recessing a portion of the PSPI layer (4) adjacent to the C4 bump (10) to form a PSPI pedestal (26) under the C4 bump (10). The method can additionally include forming an Underfill (32) abutting the PSPI pedestal (26) and the C4 bump (10), wherein the Underfill (32) and the solder (18) form an interface separated from the PSPI pedestal (26).
Abstract translation: 各种实施方案包括形成互连结构的方法以及通过这些方法形成的结构。 在一个实施方案中，一种方法可以包括：提供具有光敏聚酰亚胺（PSPI）层（4）的前体互连结构; 覆盖PSPI层的可控崩溃芯片连接（C4）突起（10）; 以及覆盖C4凸起并且接触C4凸块的一侧（20）的焊料（18）。 该方法还可以包括使与C4凸块（10）相邻的PSPI层（4）的一部分凹陷以在C4凸块（10）下形成PSPI基座（26）。 该方法还可以包括形成邻接PSPI基座（26）和C4凸块（10）的底部填充物（32），其中底部填充物（32）和焊料（18）形成与PSPI基座（26）分离的界面。
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公开(公告)号：WO2012067992A2
公开(公告)日：2012-05-24
申请号：PCT/US2011/060553
申请日：2011-11-14
Applicant: TESSERA, INC. , HABA, Belgacem
Inventor： HABA, Belgacem
IPC: H01L23/498
CPC classification number: H01L24/05 , H01L23/49838 , H01L24/03 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L25/0657 , H01L2224/03001 , H01L2224/03003 , H01L2224/0311 , H01L2224/0401 , H01L2224/04026 , H01L2224/05551 , H01L2224/05552 , H01L2224/05555 , H01L2224/05568 , H01L2224/0557 , H01L2224/05571 , H01L2224/05572 , H01L2224/05576 , H01L2224/05644 , H01L2224/05655 , H01L2224/05686 , H01L2224/0569 , H01L2224/13022 , H01L2224/13023 , H01L2224/16145 , H01L2224/16221 , H01L2224/29018 , H01L2224/29026 , H01L2224/32145 , H01L2224/32225 , H01L2225/06513 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1032 , H01L2924/10329 , H01L2924/1037 , H01L2924/1203 , H01L2924/12042 , H01L2924/1304 , H01L2924/14 , H01L2924/1433 , H01L2924/1436 , H01L2924/1437 , H01L2924/1461 , H01L2924/20107 , H01L2924/00014 , H01L2924/00
Abstract: An assembly 100 and method of making same are provided. The assembly 100 can include a first component 105 including a dielectric region 120 having an exposed surface 122, a conductive pad 134 at the surface 122 defined by a conductive element 132 having at least a portion extending in an oscillating or spiral path along the surface 122, and a an electrically conductive bonding material 140 joined to the conductive pad 134 and bridging an exposed portion 137 of the dielectric surface 122 between adjacent segments 136, 138. The conductive pad 134 can permit electrical interconnection of the first component 105 with a second component 107 having a terminal 108 joined to the pad 134 through the electrically conductive bonding material 140. The path of the conductive element 132 may or may not overlap or cross itself.
Abstract translation: 提供了组件100及其制造方法。 组件100可以包括第一部件105，第一部件105包括具有暴露表面122的电介质区域120，在表面122处的导电垫134由导电元件132限定，该导电元件132具有沿着表面122在振荡或螺旋路径中延伸的至少一部分 以及结合到导电焊盘134并桥接相邻段136,138之间的电介质表面122的暴露部分137的导电结合材料140.导电焊盘134可以允许第一部件105与第二部件 107，其具有通过导电结合材料140连接到焊盘134的端子108.导电元件132的路径可以重叠或不重叠。
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9.发明申请
公开(公告)号：WO2017048388A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/045255
申请日：2016-08-03
Applicant: MICRON TECHNOLOGY, INC.
Inventor： MARIOTTINI, Giorgio , VADHAVKAR, Sameer , HUANG, Wayne , CHANDOLU, Anilkumar , BOSSLER, Mark
IPC: H01L23/00 , H01L23/31 , H01L23/488 , H01L21/60
CPC classification number: H01L24/05 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/02126 , H01L2224/02135 , H01L2224/0219 , H01L2224/03013 , H01L2224/0346 , H01L2224/03472 , H01L2224/0361 , H01L2224/03906 , H01L2224/03912 , H01L2224/0401 , H01L2224/05009 , H01L2224/05082 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05547 , H01L2224/05553 , H01L2224/05555 , H01L2224/05565 , H01L2224/05568 , H01L2224/05644 , H01L2224/05655 , H01L2224/05684 , H01L2224/05686 , H01L2224/05687 , H01L2224/10145 , H01L2224/114 , H01L2224/11472 , H01L2224/13018 , H01L2224/13023 , H01L2224/13026 , H01L2224/13109 , H01L2224/13111 , H01L2224/94 , H01L2924/014 , H01L2924/07025 , H01L2924/3651 , H01L2224/11 , H01L2224/03 , H01L2924/00014 , H01L2924/01047 , H01L2924/053
Abstract: The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.
Abstract translation: 本技术涉及制造用于管芯到管芯和/或封装到封装互连及相关系统的凸块下金属（UBM）结构的套圈。 半导体管芯包括具有固态部件的半导体材料和至少部分延伸穿过半导体材料的互连。 在半导体材料之上形成凸块下金属（UBM）结构，并且电耦合到相应的互连。 套环围绕UBM结构的侧表面的至少一部分，并且焊料材料设置在UBM结构的顶表面上。
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公开(公告)号：WO2014149338A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/017389
申请日：2014-02-20
Applicant: ORACLE INTERNATIONAL CORPORATION
Inventor： THACKER, Hiren D. , KRISHNAMOORTHY, Ashok V. , CUNNINGHAM, John E. , ZHANG, Chaoqi
IPC: H01L21/60 , H01L23/485 , H01L23/29 , H01L23/31 , B23K3/06 , H01L21/02 , H01L25/065 , H01L21/56 , H01L21/683
CPC classification number: H01L24/14 , B23K3/0623 , H01L21/561 , H01L21/6836 , H01L23/296 , H01L23/3171 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/74 , H01L24/81 , H01L24/98 , H01L25/0657 , H01L2221/68327 , H01L2221/68381 , H01L2224/03452 , H01L2224/0361 , H01L2224/0362 , H01L2224/0401 , H01L2224/05557 , H01L2224/05558 , H01L2224/05571 , H01L2224/05573 , H01L2224/05686 , H01L2224/11005 , H01L2224/11013 , H01L2224/11015 , H01L2224/11334 , H01L2224/13099 , H01L2224/13561 , H01L2224/1357 , H01L2224/13644 , H01L2224/13686 , H01L2224/17517 , H01L2224/742 , H01L2224/81002 , H01L2224/81141 , H01L2224/81191 , H01L2224/81815 , H01L2224/94 , H01L2924/00014 , H01L2924/05432 , H01L2224/11 , H01L2224/03 , H01L2924/00012 , H01L2924/05442 , H01L2224/05552
Abstract: A multi-chip module ( MCM ) is described. This MCM includes at least two substrates that are mechanically coupled and aligned by positive and negative features on facing surfaces of the substrates. These positive and negative features may mate and self-lock with each other. The positive features may be self-populated into the negative features on at least one of the substrates using a hydrophilic layer in the negative feature. This hydrophilic layer may be used in conjunction with a hydrophobic layer surrounding the negative features on a top surface of at least one of the substrates.
Abstract translation: 描述了多芯片模块（MCM）。 该MCM包括至少两个基板，其通过在基板的相对表面上的正和负特征机械耦合和对准。 这些积极和消极的特征可以彼此交配和自锁。 可以使用负特征中的亲水层，在至少一个基板上将负面特征自身填充到负极特征中。 该亲水层可以与围绕至少一个基底的顶表面上的负特征的疏水层结合使用。
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