公开(公告)号：WO2008045589A3

公开(公告)日：2008-04-17

申请号：PCT/US2007/068339

申请日：2007-05-07

Applicant: WALKER, Andrew J.

Inventor： WALKER, Andrew J.

IPC: H01L29/788 ,  H01L27/105

Abstract: A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness such that a sensitivity parameter relating an electrical interaction between the gate electrodes of the access device and the memory device is less than a predetermined value. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings. In such an array, during programming of a nearby memory device in a NAND string, in NAND-strings not to be programmed, if inversion regions are allowed to be formed in the semiconductor layer, or if the semiconductor layer is allowed to electrically float, electrical interaction exists between the access devices and the memory devices to inhibit programming of the memory devices.

公开(公告)号：WO2005057586A3

公开(公告)日：2005-09-09

申请号：PCT/US2004040283

申请日：2004-12-02

Applicant: MATRIX SEMICONDUCTOR INC ,  CHEN EN-HSING ,  WALKER ANDREW J ,  SCHEUERLEIN ROY E ,  NALLAMOTHU SUCHETA ,  ILKBAHAR ALPER ,  FASOLI LUCA G ,  CLEEVES JAMES M

Inventor： CHEN EN-HSING ,  WALKER ANDREW J ,  SCHEUERLEIN ROY E ,  NALLAMOTHU SUCHETA ,  ILKBAHAR ALPER ,  FASOLI LUCA G ,  CLEEVES JAMES M

IPC: G11C8/08 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/0483 ,  G11C8/08 ,  G11C16/08 ,  G11C16/3418 ,  G11C16/3427

Abstract: An exemplary NAND string memory array (300) provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple series select devices at one or both ends of each NAND string reduce leakage through such select devices, for both unselected and selected NAND strings. An exemplary memory array may include series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells (400) formed above a substrate.

Abstract translation: 示例性的NAND串存储器阵列（300）提供用于半选择的存储器单元通道的电容性升压以减少半选择单元的编程干扰效应。 为了降低升压电平的漏电流劣化的影响，在NAND串的一端或两端的多个串联选择器件减少了对于未选择和选择的NAND串的这些选择器件的泄漏。 示例性存储器阵列可以包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面（400）。

公开(公告)号：WO2005057586A2

公开(公告)日：2005-06-23

申请号：PCT/US2004/040283

申请日：2004-12-02

Applicant: MATRIX SEMICONDUCTOR, INC. ,  CHEN, En-Hsing ,  WALKER, Andrew J. ,  SCHEUERLEIN, Roy E. ,  NALLAMOTHU, Sucheta ,  ILKBAHAR, Alper ,  FASOLI, Luca G. ,  CLEEVES, James M.

Inventor： CHEN, En-Hsing ,  WALKER, Andrew J. ,  SCHEUERLEIN, Roy E. ,  NALLAMOTHU, Sucheta ,  ILKBAHAR, Alper ,  FASOLI, Luca G. ,  CLEEVES, James M.

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C8/08 ,  G11C16/08 ,  G11C16/3418 ,  G11C16/3427

Abstract: An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple series select devices at one or both ends of each NAND string reduce leakage through such select devices, for both unselected and selected NAND strings. An exemplary memory array may include series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

Abstract translation: 示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。 为了降低升压电平的漏电流劣化的影响，在NAND串的一端或两端的多个串联选择器件减少了对于未选择和选择的NAND串的这些选择器件的泄漏。 示例性存储器阵列可以包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

公开(公告)号：WO2003017285A1

公开(公告)日：2003-02-27

申请号：PCT/US2002/021318

申请日：2002-08-12

Applicant: MATRIX SEMICONDUCTOR, INC. ,  WALKER, Andrew, J. ,  JOHNSON, Mark, G. ,  KNALL, N., Johan ,  KOUZNETSOV, Igor, G. ,  PETTI, Christopher, J.

Inventor： WALKER, Andrew, J. ,  JOHNSON, Mark, G. ,  KNALL, N., Johan ,  KOUZNETSOV, Igor, G. ,  PETTI, Christopher, J.

IPC: G11C17/00

CPC classification number: H01L27/11568 ,  G11C16/0466 ,  H01L21/822 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11578

Abstract: A nonvolatile memory array is provided. The array includes an array of nonvolatile memory devices, at least one driver circuit (2), and a substrate (3). The at least one driver circuit (2) is not located in a bulk monocrystalline silicon substrate (7). The at least one driver circuit may be located in a silicon on insulator substrate (3) or in a compound substrate.

Abstract translation: 提供非易失性存储器阵列。 阵列包括非易失性存储器件阵列，至少一个驱动电路（2）和衬底（3）。 至少一个驱动电路（2）不位于大块单晶硅衬底（7）中。 至少一个驱动器电路可以位于绝缘体上硅衬底（3）上或复合衬底中。

公开(公告)号：WO2007140081A3

公开(公告)日：2008-07-24

申请号：PCT/US2007068345

申请日：2007-05-07

Applicant: WALKER ANDREW J

Inventor： WALKER ANDREW J

IPC: H01L29/10

CPC classification number: H01L29/7881 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/78645 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A scalable semiconductor device is formed using control gates formed on opposite sides of a semiconductor layer. A first control gate is formed electrically isolated from a first surface of the semiconductor layer by a first dielectric layer, such that, when a first voltage is applied on the first control gate, a first depletion region is formed in the semiconductor layer opposite the first control gate. A second control gate and a third control gate are also formed, each isolated from the semiconductor region by a second dielectric layer formed on a second surface of the semiconductor layer opposite the first surface. The second and the third control gates are offset from the first control gate such that, when a second voltage is applied to the second and third control gates, depletion regions are formed opposite the second and third control gates, respectively, such that each of the depletion regions opposite the second and third control gates overlaps the first depletion region to serve as source and drain regions, when filled with mobile carriers, of a field-effect transistor to the first depletion region, which serves as a channel region of the field-effect transistor.

Abstract translation: 使用形成在半导体层的相对侧上的控制栅极形成可伸缩半导体器件。 第一控制栅极通过第一介电层与半导体层的第一表面电隔离，使得当在第一控制栅极上施加第一电压时，在与第一栅极相反的半导体层中形成第一耗尽区 控制门 还形成第二控制栅极和第三控制栅极，每个通过形成在与第一表面相对的半导体层的第二表面上的第二介电层与半导体区域隔离。 第二和第三控制栅极偏离第一控制栅极，使得当第二电压施加到第二和第三控制栅极时，耗尽区分别与第二和第三控制栅极相对形成，使得每个 与第二和第三控制栅极相对的耗尽区域与第一耗尽区域重叠，用作当场效应晶体管充满移动载流子的源极和漏极区域到第一耗尽区域时，其用作场效应晶体管的沟道区域， 效应晶体管。

公开(公告)号：WO2007087097A3

公开(公告)日：2007-08-02

申请号：PCT/US2006/061875

申请日：2006-12-11

Applicant: WALKER, Andrew J.

Inventor： WALKER, Andrew J.

IPC: G11C11/34 ,  G11C16/04

Abstract: A memory circuit and a method is provided for programming a dual-gate memory cell without program disturb in other dual-gate memory cells in the memory circuit coupled by common word lines (see FIG 3) In one embodiment, the method uses a self-boosting technique on unselected memory cells having source and drain regions in the shared semiconductor layer between their memory devic and their access devices brought to a predetermined voltage close to the threshold voltage of their access devices, thereby rendering th source and drain regions substantially floating In some embodiments, the source and drain regions are brought to the predetermined voltage via one or more select gates and intervening access gates In some embodiments, the select gates are overdriven (see FIGs 7- 12).

公开(公告)号：WO2007018821A3

公开(公告)日：2007-02-15

申请号：PCT/US2006/025438

申请日：2006-06-29

Applicant: WALKER, Andrew, J.

Inventor： WALKER, Andrew, J.

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/76 ,  H01L29/788

Abstract: A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness, such that when a pass voltage is applied to the gate electrode of the access device, the access device and the memory device remains isolated, such that the charge stored in the memory device is unaffected by the pass voltage. The pass voltage is determined from a range of voltages, when applied to the access device, has no effect on the threshold voltage of the memory device. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings. In such an array, during programming of a nearby memory device in a NAND string, in NAND-strings not to be programmed, if inversion regions are allowed to be formed in the semiconductor layer, or if the semiconductor layer is allowed to electrically float, electrical interaction exists between the access devices and the memory devices to inhibit programming of the memory devices.

公开(公告)号：WO2005057585A3

公开(公告)日：2005-08-18

申请号：PCT/US2004040318

申请日：2004-12-02

Applicant: MATRIX SEMICONDUCTOR INC ,  CHEN EN-HSING ,  WALKER ANDREW J ,  SCHEUERLEIN ROY E ,  NALLAMOTHU SUCHETA ,  ILKBAHAR ALPER ,  FASOLI LUCA G

Inventor： CHEN EN-HSING ,  WALKER ANDREW J ,  SCHEUERLEIN ROY E ,  NALLAMOTHU SUCHETA ,  ILKBAHAR ALPER ,  FASOLI LUCA G

IPC: G11C5/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483

Abstract: An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings.

Abstract translation: 示范性NAND串行存储器阵列提供半选择存储器单元信道的电容式升压以减少半选择单元的编程干扰效应。 为了减小升压电平的泄漏电流降级的影响，采用更短持续时间的多个编程脉冲来限制这样的泄漏电流可能降低未选NAND串内的电压的时间段。 另外，在每个NAND串的一端或两端处的多个串联选择器件进一步确保通过这种选择器件的泄漏减少，对于未选择和选择的NAND串二者。

公开(公告)号：WO2005057585A2

公开(公告)日：2005-06-23

申请号：PCT/US2004/040318

申请日：2004-12-02

Applicant: MATRIX SEMICONDUCTOR, INC. ,  CHEN, En-Hsing ,  WALKER, Andrew J. ,  SCHEUERLEIN, Roy E. ,  NALLAMOTHU, Sucheta ,  ILKBAHAR, Alper ,  FASOLI, Luca G.

Inventor： CHEN, En-Hsing ,  WALKER, Andrew J. ,  SCHEUERLEIN, Roy E. ,  NALLAMOTHU, Sucheta ,  ILKBAHAR, Alper ,  FASOLI, Luca G.

IPC: G11C16/00

CPC classification number: G11C16/10 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483

Abstract: An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings.

Abstract translation: 示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。 为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。 此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。

公开(公告)号：WO0215277A8

公开(公告)日：2002-07-11

申请号：PCT/US0125092

申请日：2001-08-13

Applicant: MATRIX SEMICONDUCTOR INC ,  LEE THOMAS H ,  SUBRAMANIAN VIVEK ,  CLEEVES JAMES M ,  WALKER ANDREW J ,  PETTI CHRISTOPHER ,  KOUZNETZOV IGOR G ,  JOHNSON MARK G ,  FARMWALD PAUL M ,  HERNER BRAD

Inventor： LEE THOMAS H ,  SUBRAMANIAN VIVEK ,  CLEEVES JAMES M ,  WALKER ANDREW J ,  PETTI CHRISTOPHER ,  KOUZNETZOV IGOR G ,  JOHNSON MARK G ,  FARMWALD PAUL M ,  HERNER BRAD

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/06 ,  H01L27/10 ,  H01L27/112 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L29/861 ,  H01L27/115 ,  G11C11/34 ,  H01L27/14

CPC classification number: H01L27/11582 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5612 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/8221 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0626 ,  H01L29/0661 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7391 ,  H01L29/78642 ,  H01L29/7881 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L29/861 ,  H01L29/8616

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract translation: 提供了包括多个器件层级的电荷存储器件的单片三维阵列，其中通过化学机械抛光平面化两个连续器件层级之间的至少一个表面。