公开(公告)号：WO2008014633A1

公开(公告)日：2008-02-07

申请号：PCT/CN2006/001507

申请日：2006-06-29

Applicant: INTEL CORPORATION ,  TANG, John, J. ,  XU, Henry ,  SAKAMOTO, Shinichi

Inventor： TANG, John, J. ,  XU, Henry ,  SAKAMOTO, Shinichi

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/60

CPC classification number: H01L23/49811 ,  H01L21/50 ,  H01L21/56 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5226 ,  H01L24/09 ,  H01L24/24 ,  H01L24/25 ,  H01L24/43 ,  H01L24/82 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L2021/60007 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/435 ,  H01L2224/43985 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/85138 ,  H01L2224/85815 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/48

Abstract: Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.

Abstract translation: 本发明的一些实施例包括在支撑件和附接到支撑件的至少一个模具之间的连接结构。 模具包括在模具的表面上的多个管芯接合焊盘。 连接结构包括多个通孔和凹槽组合。 导电材料形成在通孔和沟槽组合中，以提供管芯接合焊盘和支撑件上的接合焊盘之间的连接。 描述和要求保护其他实施例。

公开(公告)号：WO2016175654A2

公开(公告)日：2016-11-03

申请号：PCT/NL2016/050296

申请日：2016-04-26

Applicant: NEDERLANDSE ORGANISATIE VOOR TOEGEPAST-NATUURWETENSCHAPPELIJK ONDERZOEK TNO

Inventor： HENDRIKS, Rob Jacob ,  VAN DEN ENDE, Daan Anton ,  SMITS, Edsger Constant Pieter

IPC: H01L21/60 ,  H01L21/67 ,  H01L21/683 ,  H01L21/98

CPC classification number: H01L21/67356 ,  H01L21/67751 ,  H01L21/683 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L24/97 ,  H01L2021/60007 ,  H01L2221/68354 ,  H01L2221/68381 ,  H01L2224/1131 ,  H01L2224/1132 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/75252 ,  H01L2224/75253 ,  H01L2224/7526 ,  H01L2224/75502 ,  H01L2224/75611 ,  H01L2224/7565 ,  H01L2224/75702 ,  H01L2224/75753 ,  H01L2224/75804 ,  H01L2224/75824 ,  H01L2224/759 ,  H01L2224/7598 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81224 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A method and apparatus for soldering a chip (1a) to a substrate (3). A chip carrier (8) is provided between a flash lamp (5) and the substrate (3). The chip (1a) is attached to the chip carrier (8) on a side of the chip carrier (8) facing the substrate (3). A solder material (2) is disposed between the chip (1a) and the substrate (3). The flash lamp (5) generates a light pulse (6) for heating the chip (1a). The heating of the chip (1a) causes the chip (1a) to be released from the chip carrier (8) towards the substrate (3). The solder material (2) is at least partially melted by contact with the heated chip (1a) for attaching the chip (1a) to the substrate (3).

Abstract translation: 一种将芯片（1a）焊接到基板（3）上的方法和装置。 芯片载体（8）设置在闪光灯（5）和基板（3）之间。 芯片（1a）在芯片载体（8）的面向衬底（3）的一侧附着于芯片载体（8）。 在芯片（1a）和基板（3）之间设置焊料（2）。 闪光灯（5）产生用于加热芯片（1a）的光脉冲（6）。 芯片（1a）的加热使得芯片（1a）从芯片载体（8）向衬底（3）释放。 焊料材料（2）通过与加热芯片（1a）的接触而至少部分地熔化，用于将芯片（1a）附接到基板（3）。

公开(公告)号：WO2008088479A1

公开(公告)日：2008-07-24

申请号：PCT/US2007/024819

申请日：2007-12-03

Applicant: INTEL CORPORATION ,  PANG, Mengzhi ,  GURUMURTHY, Charan

Inventor： PANG, Mengzhi ,  GURUMURTHY, Charan

IPC: H01L23/12 ,  H01L21/60

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L2021/60007 ,  H01L2021/60022 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11 ,  H01L2224/1131 ,  H01L2224/13 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/8134 ,  H01L2224/81815 ,  H01L2225/1058 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H01L2924/19043 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method of forming a microelectronic package, and a package formed according to the method. The method includes: providing a microelectronic substrate including bonding pads and solder bumps on respective ones of the bonding pads; providing a microelectronic die including bumping sites thereon; providing solder caps on the bumping sites; positioning the die onto the substrate to form a die-substrate combination, positioning including placing respective ones of the solder caps on the die in registration with corresponding ones of the solder bumps on the substrate; and bonding the die to the substrate by subjecting the die-substrate combination to reflow to form solder joints from the solder caps and solder bumps.

Abstract translation: 一种形成微电子封装的方法，以及根据该方法形成的封装。 该方法包括：在相应的焊盘上提供包括焊盘和焊料凸点的微电子衬底; 提供包括其上的凸起位置的微电子模具; 在碰撞点上提供焊接帽; 将模具定位在基板上以形成模具 - 基板组合，定位包括将相应的焊料帽放置在模具上，与基板上的相应焊料凸块对准; 以及通过使所述管芯基板组合回流以从所述焊料帽和焊料凸起形成焊点而将所述管芯接合到所述衬底。