公开(公告)号：EP2406822A2

公开(公告)日：2012-01-18

申请号：EP10714121.0

申请日：2010-03-12

申请人： Tessera, Inc.

发明人： HABA, Belgacem ,  MARCUCCI, Brian

IPC分类号： H01L23/49

CPC分类号： B81B7/0006 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2223/6611 ,  H01L2224/06136 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/4809 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48464 ,  H01L2224/48471 ,  H01L2224/49052 ,  H01L2224/49174 ,  H01L2224/49176 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1579 ,  H01L2924/19107 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00011 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A microelectronic assembly can include a microelectronic device, e.g., semiconductor chip, connected together with an interconnection element, e.g., substrate, the latter having signal contacts and reference contacts. The reference contacts can be connectable to a source of reference potential such as ground or a voltage source other than ground such as a voltage source used for power. Signal conductors, e.g., signal wirebonds can be connected to device contacts exposed at a surface of the microelectronic device. Reference conductors, e.g., reference wirebonds can be provided, at least one of which can be connected with two reference contacts of the interconnection element. The reference wirebond can have a run which extends at an at least substantially uniform spacing from a signal conductor, e.g., signal wirebond that is connected to the microelectronic device over at least a substantial portion of the length of the signal conductor. In such manner a desired impedance may be achieved for the signal conductor.

摘要翻译： 一种微电子组件可以包括一个微电子器件，例如半导体芯片，在互连元件，E. G.，基板用连接在一起，后者具有信号触头和参考触点。 基准触点可连接到参考电势源：如地面或不同于地电压源：诸如用于电源的电压源。 信号导体，E. G.，信号引线键合可以被连接到在所述微电子器件的表面露出装置触点。 参考导体，E. G.，可以提供参考线键合，其中至少一种可以与互连元件的两个参考触点相连。 参考引线接合可以在从信号导体，E. G.，信号线接合也被连接到微电子器件通过信号导体的长度的至少一个实质性的部分，用于至少基本上均匀的间隔延伸的运行。 在寻求一种方式所需的阻抗，可以实现为信号导体。

公开(公告)号：EP1028465A3

公开(公告)日：2001-05-16

申请号：EP00102456.1

申请日：2000-02-04

申请人： Kabushiki Kaisha Toyoda Jidoshokki Seisakusho

发明人： Sofue, Kenichi ,  Yoshiyama, Hiromitsu ,  Fukatsu, Toshinari ,  Nagase, Toshiaki

IPC分类号： H01L25/07

CPC分类号： H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49176 ,  H01L2224/85399 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01057 ,  H01L2924/13091 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： A plurality of MOS transistors are arranged on the top surface of a conductor substrate which is a drain electrode. The drain contact of each MOS transistor is connected to the conductor substrate. The source contact of each MOS transistor is connected to the output conductor path which is a source electrode through a bonding wire. The gate contact of each MOS transistor is connected to a drive signal conductor path which is a gate electrode through a bonding wire. The source contacts of the MOS transistors are interconnected through a bridge electrode and a bonding wire.

摘要翻译： 在作为漏电极的导体基板的顶面上配置有多个MOS晶体管。 每个MOS晶体管的漏极接触连接到导体衬底。 每个MOS晶体管的源极接触通过接合线连接到作为源电极的输出导体路径。 每个MOS晶体管的栅极接触通过接合线连接到作为栅电极的驱动信号导体路径。 MOS晶体管的源极触点通过桥电极和接合线互连。

公开(公告)号：EP1035585A3

公开(公告)日：2000-10-25

申请号：EP00104774.5

申请日：2000-03-06

申请人： ROBERT BOSCH GMBH

发明人： Kern, Stefan

IPC分类号： H01L23/66

CPC分类号： H01L23/49838 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/48 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2224/05599

摘要： Eine Bondverbindung, die für sehr hohe Frequenzen gute breitbandige Anpassungs- und Übertragungseigenschaften aufweist, besteht darin, daß zwei auf benachbarten Substraten (1, 2) verlaufende Streifenleitungen (3, 4) mit vergrößerten, kapazitiv wirkenden Anschlußflächen (5, 6) enden und die Anschlußflächen (5, 6) beider Streifenleitungen (3, 4) über einen oder mehrere Bonddrähte (7, 8, 9) miteinander kontaktiert sind. Vor den Anschlußflächen (5, 6) der Streifenleitungen (3, 4) ist jeweils ein induktiv wirkendes Leitungsstück (10, 11) mit einer geringeren Leiterbreite als die Streifenleitungen (3, 4) eingefügt.

公开(公告)号：EP1028465A2

公开(公告)日：2000-08-16

申请号：EP00102456.1

申请日：2000-02-04

申请人： Kabushiki Kaisha Toyoda Jidoshokki Seisakusho

发明人： Sofue, Kenichi ,  Yoshiyama, Hiromitsu ,  Fukatsu, Toshinari ,  Nagase, Toshiaki

IPC分类号： H01L25/07

CPC分类号： H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49176 ,  H01L2224/85399 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01057 ,  H01L2924/13091 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： A plurality of MOS transistors are arranged on the top surface of a conductor substrate which is a drain electrode. The drain contact of each MOS transistor is connected to the conductor substrate. The source contact of each MOS transistor is connected to the output conductor path which is a source electrode through a bonding wire. The gate contact of each MOS transistor is connected to a drive signal conductor path which is a gate electrode through a bonding wire. The source contacts of the MOS transistors are interconnected through a bridge electrode and a bonding wire.

摘要翻译： 多个MOS晶体管被布置在作为漏电极的导体衬底的顶表面上。 每个MOS晶体管的漏极触点连接到导体衬底。 每个MOS晶体管的源极接点通过接合线连接到作为源电极的输出导体路径。 每个MOS晶体管的栅极接点通过接合线连接到作为栅电极的驱动信号导体路径。 MOS晶体管的源极触点通过桥电极和键合线相互连接。

公开(公告)号：EP0318209B1

公开(公告)日：1994-06-15

申请号：EP88310884.7

申请日：1988-11-18

申请人： AT&T Corp.

发明人： Thomas, Donald A.

IPC分类号： H01L21/60

CPC分类号： H01L24/85 ,  H01L23/4985 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48137 ,  H01L2224/4899 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2224/85203 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/117 ,  H05K1/144 ,  H05K3/361 ,  Y10T29/49162 ,  Y10T156/1089 ,  Y10T156/1092 ,  Y10T156/1093 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

公开(公告)号：EP2362417A3

公开(公告)日：2012-05-23

申请号：EP11004204.1

申请日：2009-09-02

申请人： Linear Technology Corporation

发明人： Pruitt, David, A.

IPC分类号： H01L23/64 ,  H01L23/495 ,  H01F19/08

CPC分类号： H01F19/08 ,  H01F38/14 ,  H01F2019/085 ,  H01F2027/2814 ,  H01L23/48 ,  H01L23/4952 ,  H01L23/642 ,  H01L23/645 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/072 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/4823 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48491 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/49052 ,  H01L2224/4912 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2224/4943 ,  H01L2224/85455 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/48824

摘要： A semiconductor device (200) configured to provide current and voltage isolation inside an integrated circuit package, the semiconductor device comprising:
a lead frame (210) including a first set of leads (220,222,224,226) and a second set of leads (230,232,234,236), the first set of leads being isolated from the second set of leads;
a semiconductor die (240) positioned on the lead frame (210);
an isolating block (250) positioned on the semiconductor die;
a first interconnect coil (202) formed by a first set of wires (260,262,264,266), the semiconductor die, and the first set of leads; and
a second interconnect coil (204) isolated from the first interconnect coil and formed by a second set of wires (280,282,284,286), the isolating block, and the second set of leads.

公开(公告)号：EP2393111A1

公开(公告)日：2011-12-07

申请号：EP11168190.4

申请日：2011-05-31

申请人： NXP B.V.

发明人： Blednov, Igor

IPC分类号： H01L23/49 ,  H01L23/52 ,  H01L23/66 ,  H01L27/04 ,  H03F1/56 ,  H03F1/02

CPC分类号： H03F1/565 ,  H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/49111 ,  H01L2224/4917 ,  H01L2224/49174 ,  H01L2224/49176 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03F1/0288 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A bond wire circuit includes bond wires arranged relatively to provide a selected inductance. In connection with various example embodiments, respective bond wire loops including forward and return current paths are arranged orthogonally. Each loop includes a forward bond wire connecting an input terminal with an intermediate terminal, and a return bond wire connecting the intermediate terminal to an output terminal. The return bond wires generally mitigate return current flow from the intermediate terminal in an underlying substrate. In some implementations, the loops are arranged such that current flowing in each of the respective loops generates equal and self-cancelling current in the other of the respective loops.

摘要翻译： 接合线电路包括相对于提供所选择的电感布置的接合线。 结合各种示例实施例，包括正向和回流电流路径的各个接合线环路被布置成正交。 每个环路包括将输入端子与中间端子连接的正向接合线以及将中间端子连接到输出端子的返回接合线。 返回接合线通常减轻来自底层衬底中的中间端子的回流电流。 在一些实施方案中，循环被布置成使得在每个相应回路中流动的电流在相应回路中的另一个中产生相等的自消除电流。

公开(公告)号：EP2362417A2

公开(公告)日：2011-08-31

申请号：EP11004204.1

申请日：2009-09-02

申请人： Linear Technology Corporation

发明人： Pruitt, David, A.

IPC分类号： H01L25/07 ,  H01L23/64 ,  H01L23/495

CPC分类号： H01F19/08 ,  H01F38/14 ,  H01F2019/085 ,  H01F2027/2814 ,  H01L23/48 ,  H01L23/4952 ,  H01L23/642 ,  H01L23/645 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/072 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/4823 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48491 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/49052 ,  H01L2224/4912 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2224/4943 ,  H01L2224/85455 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/48824

摘要： A semiconductor device configured to provide current and voltage isolation inside an integrated circuit package, the semiconductor device comprising:
a lead frame including a first set of leads and a second set of leads, the first set of leads being isolated from the second set of leads;
a semiconductor die positioned on the lead frame;
an isolating block positioned on the semiconductor die;
a first interconnect coil formed by a first set of wires, the semiconductor die, and the first set of leads; and
a second interconnect coil isolated from the first interconnect coil and formed by a second set of wires, the isolating block, and the second set of leads.

摘要翻译： 一种半导体器件（200），被配置为在集成电路封装内提供电流和电压隔离，所述半导体器件包括：引线框架（210），包括第一组引线（220,222,224,226）和第二组引线（230,232,234,236），所述引线框架 第一组引线与第二组引线隔离; 定位在引线框架（210）上的半导体管芯（240）; 位于所述半导体管芯上的隔离块（250）; 由第一组线（260,262,264,266）形成的第一互连线圈（202），所述半导体管芯和所述第一组引线; 以及与第一互连线圈隔离并由第二组电线（280,282,284,286），隔离块和第二组引线形成的第二互连线圈（204）。

公开(公告)号：EP1035585B1

公开(公告)日：2011-05-11

申请号：EP00104774.5

申请日：2000-03-06

申请人： Ericsson AB

发明人： Kern, Stefan

IPC分类号： H01L23/66

CPC分类号： H01L23/49838 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/48 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2224/05599

公开(公告)号：EP1028465B1

公开(公告)日：2007-01-03

申请号：EP00102456.1

申请日：2000-02-04

申请人： KABUSHIKI KAISHA TOYOTA JIDOSHOKKI

发明人： Sofue, Kenichi ,  Yoshiyama, Hiromitsu ,  Fukatsu, Toshinari ,  Nagase, Toshiaki

IPC分类号： H01L25/07

CPC分类号： H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49176 ,  H01L2224/85399 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01057 ,  H01L2924/13091 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： A plurality of MOS transistors are arranged on the top surface of a conductor substrate which is a drain electrode. The drain contact of each MOS transistor is connected to the conductor substrate. The source contact of each MOS transistor is connected to the output conductor path which is a source electrode through a bonding wire. The gate contact of each MOS transistor is connected to a drive signal conductor path which is a gate electrode through a bonding wire. The source contacts of the MOS transistors are interconnected through a bridge electrode and a bonding wire.