公开(公告)号：EP1698033A2

公开(公告)日：2006-09-06

申请号：EP04817915.4

申请日：2004-12-22

Applicant: X2Y Attenuators, L.L.C.

Inventor： ANTHONY, David ,  ANTHONY, Anthony ,  ANTHONY, William, M. ,  MUCCIOLI, James ,  NEIFELD, Richard, A.

IPC: H02H9/00

CPC classification number: H01G4/35 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01P1/203 ,  H05K1/0233 ,  H05K2201/09254 ,  H05K2201/0969 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/1006 ,  H05K2201/10454 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

Abstract: An energy conditioner structure comprising a first electrode (120), a second electrode (80), and a shield structure (70, 110, 150) provides improved energy conditioning in electrical circuits. The structures may exist as discrete components or part of an integrated circuit. The shield structure in the energy conditioner structure does not electrically connect to any circuit element.

公开(公告)号：EP1248503A4

公开(公告)日：2006-08-09

申请号：EP00987672

申请日：2000-12-21

Applicant: TOYO KOHAN CO LTD

Inventor： SAIJO KINJI ,  OHSAWA SHINJI ,  OKAMOTO HIROAKI ,  YOSHIDA KAZUO

IPC: H05K1/02 ,  H05K3/06 ,  H05K3/46

CPC classification number: H05K1/0221 ,  H05K3/062 ,  H05K3/4647 ,  H05K2201/0361 ,  H05K2201/09254 ,  H05K2203/0384 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A structure of a multilayer printed wiring board having a wiring lead-out port can be easily formed. A large number of products can be easily manufactured with good size reproducibility. A method of manufacturing the same is also are disclosed. The multilayer printed wiring board is characterized by having a signal circuit conductor perfectly covered by an earth circuit in its inside and a wiring lead-out port. A signal circuit conductor having a branch pattern is preferable. The multilayer printed wiring board is manufactured by selectively etching the copper of a cladding sheet manufactured by bonding a copper foil to a nickel foil with 0.1 - 3% draft and forming a signal circuit conductor perfectly covered by an earth circuit and the wiring lead-out port.

公开(公告)号：EP1455557A3

公开(公告)日：2006-01-04

申请号：EP03023937.0

申请日：2003-10-22

Applicant: ROBERT BOSCH GMBH

Inventor： Roozenbeck, Herman ,  Bayer, Uwe

IPC: H05K1/02

CPC classification number: H05K1/0216 ,  H05K1/0231 ,  H05K1/115 ,  H05K1/117 ,  H05K1/18 ,  H05K2201/0715 ,  H05K2201/09254 ,  H05K2201/09318 ,  H05K2201/09345 ,  H05K2201/09627 ,  H05K2201/10689

Abstract: Die vorliegende Erfindung stellt eine Trägervorrichtung (10) für elektrische Bauelemente bereit mit: einer ersten leitfähigen Ebene (23') zum Bereitstellen eines Bezugspotentials (23); und mindestens einer elektrisch von der ersten Ebene (23') isolierten zweiten Ebene (11') mit strukturierten Leitungen (11) zum Anbinden elektrischer Anschlusseinrichtungen (12) externer Bauelemente und zum Anbinden interner Bauelemente auf der Trägervorrichtung (10), wobei die Leitungen (11) zum Anbinden elektrischer Anschlusseinrichtungen (12) externer analoger Bauelemente und/oder Sensoren Bezugspotentialleitungen (16, 17) aufweisen, welche sich an einem ersten Stempunkt (18) sammeln, und die Leitungen (11) zum Anbinden interner Bauelemente Bezugspotentialleitungen (19, 20, 21) aufweisen, welche sich an einem zweiten Sternpunkt (22) sammeln und über mindestens eine Durchkontaktierungseinrichtung (23") mit der ersten Ebene (23') galvanisch gekoppelt sind und/oder die Durchkontaktierungseinrichtung (23") den ersten und/oder zweiten Stempunkt (18, 22) bildet.

公开(公告)号：EP1083779A4

公开(公告)日：2004-08-25

申请号：EP99919584

申请日：1999-05-13

Applicant: IBIDEN CO LTD

Inventor： HIROSE NAOHIRO ,  KARIYA TAKASHI ,  MORI YOJI

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/18 ,  H05K3/24 ,  H05K3/38 ,  H05K3/46

CPC classification number: H01R9/09 ,  H01L23/12 ,  H01L23/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H05K1/0256 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/115 ,  H05K1/116 ,  H05K3/184 ,  H05K3/241 ,  H05K3/382 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09272 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2201/10734 ,  H05K2203/0594 ,  Y10T29/49155 ,  Y10T29/49194 ,  Y10T428/31504

Abstract: A printed circuit board, wherein a fillet (F) is added to a portion which is a crossing (X) of wiring patterns (58b, 58c, 58d) and which forms an angle portion (C) of not larger than 90° to form a wiring pattern (58). The presence of the added fillet (F) prevents a wiring pattern at the crossing (X) from becoming thin and therefore the occurrence of a broken wire, non-concentration of stress on the crossing (X) does not cause broken wire at the wiring patterns and no bubbles remain between the crossing (X) of the wiring patterns and an interlayer resin insulation layer to enhance the reliability of the printed circuit board.

Abstract translation: 一种印刷电路板，其中在布线图形（58b，58c，58d）的交叉部分（X）上形成角度部分（C）不大于90°的部分加上圆角（F）以形成 布线图案（58）。 添加的圆角（F）的存在防止了交叉点（X）处的布线图变薄，因此断线的发生，交叉点（X）上的应力未集中不会导致布线处的断线 在布线图形的交叉点（X）和层间树脂绝缘层之间留有图案且没有气泡，以提高印刷电路板的可靠性。

公开(公告)号：EP1047146A3

公开(公告)日：2002-03-13

申请号：EP00108262.7

申请日：2000-04-14

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hidaka, Seiji, c/o (A170) Intell. Prop. Dept. ,  Ota, Michiaki c/o (A170) Intell. Prop. Dept. ,  Abe, Shin c/o (A170) Intell. Prop. Dept.

IPC: H01P1/203 ,  H01P3/08 ,  H01P7/08

CPC classification number: H01P3/081 ,  H01P1/203 ,  H01P1/2039 ,  H01P7/082 ,  H05K1/0239 ,  H05K1/0242 ,  H05K2201/09254 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/09781

Abstract: A transmission line, a resonator, a filter, a duplexer, and a communication apparatus efficiently minimize power losses due to edge effects, thereby having superior loss-reduction characteristics. A continuous line (12) and a plurality of thin lines (2) each having a predetermined length and branching from both sides of the continuous line (12) are formed on a dielectric substrate (1). According to this, substantial edges of the individual thin lines (2) do not exist, and losses due to edge effects can be efficiently minimized.

Abstract translation: 传输线具有一条连续线（12）和几根细长线（2），每根细长线从连续线分支，每条线具有预定长度。 细线的分支方向相对于连续线倾斜。 所有细线连接，而连续线连接每条细线的相同部分。

公开(公告)号：EP0657797A2

公开(公告)日：1995-06-14

申请号：EP94117661.2

申请日：1994-11-09

Applicant: International Business Machines Corporation

Inventor： Dell, Timothy Jay ,  Feng, George Cheng-Cwo ,  Kellogg, Mark William

IPC: G06F1/10

CPC classification number: H05K1/0246 ,  G06F1/10 ,  G11C7/22 ,  H05K1/117 ,  H05K2201/09254 ,  H05K2201/10022 ,  H05K2201/10689

Abstract: A packaging assembly for semiconductor memory modules using synchronous clocking signals distributed to each module within a package. The clock distribution network on the assembly is characterized by including a transmission line termination means, preferably a resistor, coupled immediately adjacent to one of the assembly input pins.

Abstract translation: 一种用于半导体存储器模块的封装组件，其使用分配到封装内的每个模块的同步时钟信号。 组件上的时钟分配网络的特征在于包括一个传输线终端装置，最好是一个电阻器，它们紧邻其中一个装配输入管脚。

公开(公告)号：EP0519740A3

公开(公告)日：1993-02-24

申请号：EP92305658.4

申请日：1992-06-19

Applicant: Compaq Computer Corporation

Inventor： Abernathy, Michael G. ,  Fletcher, Angie M. ,  Santeler, Paul ,  Thoma III, Roy E.

IPC: H05K1/00 ,  G06F1/16

CPC classification number: H05K1/0216 ,  H05K1/0237 ,  H05K2201/09254 ,  H05K2201/10689 ,  Y10T307/492

Abstract: An electrical system wherein the electrical conductive traces on the circuit boards are routed to achieve a balanced net to reduce noise caused by transmission line reflections. A trace (202,216,248,274) is routed from the source terminal (200,214,236,260) of the net to a balanced junction (204,218,238,288) wherein if there are an odd number of load terminals, or loads, the balanced junction is located at one of the loads (204,238). The remaining loads are grouped into branches wherein each branch includes an equal number of loads. A trace is routed between each of the loads of each branch to serially connect the loads of each branch together, or, a trace is routed from a center one of the branch loads to each of the remaining branch loads, forming subbranches. In an alternate embodiment, a balanced subbranch is developed. The balanced load is connected to a pseudo-balanced load, which further receives an equal number of branches. The 3 pseudo-balanced load is then connected to another pseudo-balanced load, which may also receive an equal number of branches. This pseudo-balanced load is connected to the source. In another alternative, two balanced subbranches have their balanced loads connected to a central balanced load. This balanced load may receive even further numbers of equal branches. The balanced load is connected to the source.

公开(公告)号：EP0403643A4

公开(公告)日：1991-07-03

申请号：EP90902060

申请日：1990-01-10

Applicant: L.E.A. DYNATECH

Inventor： ROZANSKI, ROBERT, D. ,  MEDLOCK, JAMES, ROGER, III ,  LARSON, STEPHEN, F.

IPC: H02B1/20 ,  H02H9/04 ,  H05K1/02 ,  H05K9/00 ,  H02B1/00 ,  H05K1/16

CPC classification number: H05K1/0254 ,  H02H9/044 ,  H05K9/0066 ,  H05K2201/09254 ,  H05K2201/09809 ,  H05K2201/10272

Abstract: A device for uniformly distributing current and voltage comprises first (16) and second terminals (26), a first electrical bus (14) electrically connected to the first terminal, a second electrical bus (24) electrically isolated from the first electrical bus and electrically connected to the second terminal, a plurality of electrical components (40) connected between the first and second buses so as to form a plurality of circuit paths of equal length, each circuit path running between the first terminal, the first electrical bus, one of the circuit components, the second electrical bus, and the second terminal. The plurality of electrical components are connected to the first and second buses at locations which are equidistant from the first and second terminals, respectively.

公开(公告)号：EP3386276A1

公开(公告)日：2018-10-10

申请号：EP15909692.4

申请日：2015-11-30

Applicant: Renesas Electronics Corporation

Inventor： TSUKUDA, Tatsuaki ,  NAKAHARA, Akihiro

IPC: H05K1/02

CPC classification number: H05K1/0231 ,  H01G4/248 ,  H01G4/30 ,  H01L25/16 ,  H05K1/02 ,  H05K1/11 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/10015 ,  H05K2201/10378

Abstract: An electronic device according to one embodiment includes a wiring substrate, the wiring substrate having a first wiring connected to a first external terminal and a second wiring connected to a second external terminal and extending along the first wiring. Additionally, the above electronic device has a semiconductor device mounted on the above wiring substrate and electrically connected to each of the first and second wirings. Further, the above electronic device has a capacitor mounted on the above wiring substrate and electrically connected to the semiconductor device via each of the above first and second wirings. Furthermore, a distance between the above semiconductor device and capacitor is shorter than a distance between each of the above first and second external terminals and the above capacitor.

公开(公告)号：EP3245853B1

公开(公告)日：2018-09-26

申请号：EP16704956.8

申请日：2016-01-11

Applicant: Qualcomm Incorporated

Inventor： SUBRAMANIAN, Yokesh

IPC: H05K1/02 ,  G11C5/02

CPC classification number: H05K1/0213 ,  G11C5/025 ,  H05K1/0243 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/025 ,  H05K1/18 ,  H05K2201/09227 ,  H05K2201/09254

Abstract: A method for propagating a signal from an output driver on a PCB to a number of chips on the PCB. The signal is propagated from a first transmission line connected to the output driver, to a second transmission line connected to the first transmission line and a first chip, and to a third transmission line connected to the first transmission line and a second chip. The second transmission line has a length greater than or equal to 10 times the length of the first transmission line, and the third transmission line has a length greater than or equal to 10 times the length of the first transmission line. The lengths of the first transmission line, the second transmission line, and the third transmission line cause a reduction in reflections of the signal due to a change in impedance at a junction of the first, second, and third transmission lines.