公开(公告)号：EP1843650A2

公开(公告)日：2007-10-10

申请号：EP07013524.9

申请日：1999-07-30

Applicant: IBIDEN CO., LTD.

Inventor： Hirose, Naohiro ,  Noda, Kouta ,  Segawa, Hiroshi ,  En, Honjin ,  Tsukada, Kiyotaka ,  Ishida, Naoto ,  Asano, Kouji ,  Shouda, Atsushi

IPC: H05K3/46 ,  H05K3/38

CPC classification number: H05K3/4652 ,  B23K26/389 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0201 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/28 ,  H05K3/381 ,  H05K3/383 ,  H05K3/384 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0358 ,  H05K2201/062 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/09881 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0554 ,  H05K2203/0773 ,  H05K2203/107 ,  H05K2203/121 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A multilayered printed circuit board comprising: a substrate (330) on which a conductive circuit (334) is formed; an interlayer insulating resin layer (350) formed on the conductive circuit (334); an opening (348) for forming a via hole (360) formed in the interlayer insulating resin layer (350); and another conductive circuit (358) including a via hole (360) and formed on the interlayer insulating resin layer (350), wherein
the surface of the conductive circuit (334) is subjected to a coarsening process using etching solution containing cupric complex and organic acid, and
stripe pits and projections are formed on the inner wall of the opening (348) for forming the via hole (360).

公开(公告)号：EP1827068A3

公开(公告)日：2007-10-03

申请号：EP07075317.3

申请日：1998-01-23

Applicant: IBIDEN CO., LTD.

Inventor： Takada, Masaru c/o Ibiden Co., Ltd. ,  Tsukada, Kiyotaka c/o Ibiden Co., Ltd. ,  Kobayashi, Hiroyuki c/o Ibiden Co., Ltd. ,  Minoura, Hisashi c/o Ibiden Co., Ltd. ,  Ukai, Yoshikazu c/o Ibiden Co., Ltd. ,  Kondo, Mitsuhiro c/o Ibiden Co., Ltd.

IPC: H05K3/40 ,  H05K3/46

CPC classification number: H05K3/4652 ,  H01L21/486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/116 ,  H05K1/182 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/3468 ,  H05K3/3484 ,  H05K3/385 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/041 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: A printed wiring board (802) comprising an insulating substrate (806), a conductor pattern formed on a surface of the insulating substrate (806), a solder filling hole (801) passing through the insulating substrate (806) and arriving at an upper surface of the conductor pattern (851) and a solder (807) filled in the solder filling hole (801), characterized in that the insulating substrate (806) includes fibers (861) therein, and end portions (863) of the fibers (861) protrude from a wall face (810) of the solder filling hole (801) and encroach into the solder (807).

Abstract translation: 一种印刷线路板（802），包括：绝缘基板（806）;在绝缘基板（806）的表面上形成的导体图案;贯通绝缘基板（806）并到达上部 （801）和填充在所述焊料填充孔（801）中的焊料（807），其特征在于，所述绝缘基底（806）中包括纤维（861），所述纤维（861）的端部（863） 861）从焊料填充孔（801）的壁面（810）突出并侵入到焊料（807）中。

公开(公告)号：EP1827069A2

公开(公告)日：2007-08-29

申请号：EP07075315.7

申请日：1998-01-23

Applicant: IBIDEN CO., LTD.

Inventor： Takada, Masaru, c/o Ibiden Co., Ltd. ,  Tsukada, Kiyotaka, c/o Ibiden Co., Ltd. ,  Kobayashi, Hiroyuki, c/o Ibiden Co., Ltd. ,  Minoura, Hisashi, c/o Ibiden Co., Ltd. ,  Ukai, Yoshikazu, c/o Ibiden Co., Ltd. ,  Kondo, Mitsuhiro, c/o Ibiden Co., Ltd.

IPC: H05K3/46

CPC classification number: H05K3/4652 ,  H01L21/486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/116 ,  H05K1/182 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/3468 ,  H05K3/3484 ,  H05K3/385 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/041 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: In the production of a printed wiring board comprising innerlayer conductor circuits 161, 131 arranged among insulating layers 101~103 and blind via-holes 141, 142 formed from an outermost surface of the insulating layer toward the innerlayer conductor circuit, an opening hole 160 is previously formed in a central portion of the innerlayer conductor circuit 161 located at the bottom of the blind via-hole 141, and laser beams are irradiated from the outermost surface of the insulating layer to form the blind via-holes 141, 142. Thereafter, a metal plated film is formed on surfaces of the innerlayer conductor circuits 13, 161 and the blind via-holes 141, 142.

Abstract translation: 在包括布置在绝缘层101〜103之间的内层导体电路161,131和从绝缘层的最外表面朝向内层导体电路形成的盲通孔141,142的印刷线路板的制造中，开孔160是 预先形成在位于盲通孔141底部的内层导体电路161的中心部分，并且从绝缘层的最外表面照射激光束以形成盲通孔141,142。之后， 在内层导体电路13,161和盲通孔141,142的表面上形成金属镀膜。

公开(公告)号：EP1816905A2

公开(公告)日：2007-08-08

申请号：EP07075316.5

申请日：1998-01-23

Applicant: IBIDEN CO., LTD.

Inventor： Takada, Masaru, c/o Ibiden Co., Ltd. ,  Tsukada, Kiyotaka, c/o Ibiden Co., Ltd. ,  Kobayashi, Hiroyuki, c/o Ibiden Co., Ltd. ,  Minoura, Hisashi, c/o Ibiden Co., Ltd. ,  Ukai, Yoshikazu, c/o Ibiden Co., Ltd. ,  Kondo, Mitsuhiro, c/o Ibiden Co., Ltd.

IPC: H05K3/46

CPC classification number: H05K3/4652 ,  H01L21/486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/116 ,  H05K1/182 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/3468 ,  H05K3/3484 ,  H05K3/385 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/041 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: In the production of a printed wiring board comprising innerlayer conductor circuits 161, 131 arranged among insulating layers 101~103 and blind via-holes 141, 142 formed from an outermost surface of the insulating layer toward the innerlayer conductor circuit, an opening hole 160 is previously formed in a central portion of the innerlayer conductor circuit 161 located at the bottom of the blind via-hole 141, and laser beams are irradiated from the outermost surface of the insulating layer to form the blind via-holes 141, 142. Thereafter, a metal plated film is formed on surfaces of the innerlayer conductor circuits 13, 161 and the blind via-holes 141, 142.

Abstract translation: 一种在内层导体电路（562）上包括两个或多个绝缘层（516,518）的印刷电路板（501），从绝缘层（516）的最外表面延伸穿过两个或多个隔离层 形成在内层导体电路（562）的层（516,518）和形成在通孔（502）中的内部金属电镀膜（521），以便与内层导体电路（562）电连接到外部导体电路 ），其特征在于，具有围绕所述通孔（502）的开孔（540）的用于加强件的环形虚设焊盘（504）布置在面向所述两个或更多个绝缘层的边界部分（517）中 （516,518）彼此连接并连接到内部金属镀膜（521）。

公开(公告)号：EP0805614B1

公开(公告)日：2005-04-13

申请号：EP96938496.5

申请日：1996-11-18

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： SASAOKA, Kenji ,  ODAIRA, Hiroshi ,  FUJIWARA, Madoka ,  IKEGAYA, Fumitoshi ,  MORI, Takahiro

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/46 ,  H01L23/48

CPC classification number: H01L24/16 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/17 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/351 ,  H05K1/095 ,  H05K1/116 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09454 ,  H05K2201/0969 ,  H05K2201/09863 ,  H05K2203/1189 ,  H05K2203/1572 ,  Y10S428/901 ,  Y10T428/24917 ,  H01L2924/00

Abstract: A multilayered wiring board using conductive pillars for the interconnection of wiring layers. Since through holes are bored in the via lands of the wiring layers of the multilayered wiring board, the stress applied between the conductive pillars and wiring layers can be released at the time of connecting the conductive pillars to the via lands. Since the external side face of each conductive pillar smoothly continues to the surface of the via land at the contact section between the conductive pillar and the via land, the notch effect is relieved. Therefore, the reliability of the interconnection is secured even when a stress is applied to the connections during the manufacturing of the multilayered wiring board, and the mounting of electronic parts, etc.

公开(公告)号：EP1220591A3

公开(公告)日：2004-07-21

申请号：EP01130722.0

申请日：2001-12-21

Applicant: Denso Corporation

Inventor： Yazaki, Yoshitaro ,  Shiraishi, Yoshihiko ,  Kondo, Koji ,  Harada, Toshikazu ,  Yokochi, Tomohiro

IPC: H05K3/46 ,  H05K3/40

CPC classification number: H05K3/4632 ,  H05K1/095 ,  H05K3/4069 ,  H05K3/4617 ,  H05K2201/0129 ,  H05K2201/0272 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0425 ,  H05K2203/1131 ,  Y10T428/24917

Abstract: A heated and pressed printed wiring board (100) is made by filling via-holes formed in layers of insulating film of the wiring board (100) with an interlayer conducting material. The insulating film is stacked with conductor patterns (22), and each conductor pattern (22) closes a via hole (24). The interlayer conducting material forms a solid conducting material (51, 52) in the via holes (24) after a heating a pressing procedure. The solid conducting material (51, 52) includes two types of conducting materials. The first type of conducting material (51) includes a metal, and the second type of conductive material (52) includes an alloy formed by the metal and conductor metal of the conductor patterns (22). The conductor patterns (22) are electrically connected reliably without relying on mere mechanical contact.

Abstract translation: 通过用层间导电材料填充形成在布线板（100）的绝缘膜的层中的通孔来制造加热和压制的印刷布线板（100）。 绝缘膜与导体图案（22）堆叠，并且每个导体图案（22）封闭通孔（24）。 中间层导电材料在加热压制过程之后在通孔（24）中形成固体导电材料（51,52）。 固体导电材料（51,52）包括两种类型的导电材料。 第一类型的导电材料（51）包括金属，第二类型的导电材料（52）包括由导体图案（22）的金属和导体金属形成的合金。 导体图案（22）可靠地电连接，而不依赖于单纯的机械接触。

公开(公告)号：EP1220589A3

公开(公告)日：2004-07-21

申请号：EP01130820.2

申请日：2001-12-24

Applicant: Denso Corporation

Inventor： Yazaki, Yoshitarou ,  Yokochi, Tomohiro ,  Kondo, Koji ,  Harada, Toshikazu ,  Shiraishi, Yoshihiko

IPC: H05K3/40 ,  H05K3/46

CPC classification number: H05K3/4632 ,  H05K1/095 ,  H05K3/4069 ,  H05K3/4617 ,  H05K2201/0129 ,  H05K2201/0272 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0425 ,  H05K2203/1131 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: Conductive paste (50) containing tin particles (61) and silver particles (62) is packed in a substantially cylindrical via hole (24) formed in a thermoplastic resin film (23) that interposes between conductor patterns (22) and is hot-pressed from both sides. When the metal particles contained in the conductive paste (50) are sintered to form a unified conductive compound (51), the volume of the conductive paste (50) shrinks. Synchronously, the resin film (23) around the via-hole (24) protrudes into the via-hole (24). Therefore, the shape of the side wall on the cross-section of the conductive compound (51) provides an arch shape, and a side wall (51a) adjacent to a junction part (51b) of the conductive compound (51), which contacts the conductor pattern (22), is formed with an inclination. Therefore, it is possible to prevent the stress concentration due to deformation of the board.

Abstract translation: 导电浆料（50）含锡颗粒（61）和银颗粒（62）被装在一个通过在一个热塑性树脂膜（23）形成的孔（24）基本上为圆柱形的那样（22）的导体图案之间介于并进行热压 从bothsides。 当包含在导电膏（50）的金属颗粒烧结，以形成一个统一的导电性化合物（51），导电浆料的体积（50）收缩。 同步，所述树脂薄膜 - （23）围绕所述通孔（24）突出到所述通孔（24）。 因此，在导电化合物的横截面侧壁的形状（51）提供了一个拱形状，并且侧壁（51A）邻近于接合部分（51b）上的导电性化合物的（51）接触哪 导体图案（22）的倾斜，形成与。 因此，能够防止应力集中，由于板的变形。

公开(公告)号：EP1019986A1

公开(公告)日：2000-07-19

申请号：EP98952161.2

申请日：1998-10-07

Applicant: Dimensional Circuits Corp.

Inventor： GREGOIRE, George, D.

IPC: H01R9/09

CPC classification number: H05K3/005 ,  H05K1/095 ,  H05K1/112 ,  H05K1/115 ,  H05K3/0014 ,  H05K3/061 ,  H05K3/107 ,  H05K3/1241 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/465 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09863 ,  H05K2201/09981 ,  H05K2203/0108 ,  H05K2203/025 ,  H05K2203/041 ,  H05K2203/0746 ,  H05K2203/095 ,  H05K2203/1189 ,  H05K2203/1572 ,  Y10T29/49126 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: A wiring board construction (10) includes at least one microvia (12) disposed in a base substrate (14) and includes a deep imprinted cup shaped in the top surface thereof (24). A conductor material is disposed within the recess (26), and has a portion disposed at the bottom thereof. A conductor disposed at a bottom surface of the substrate opposite to the conductor material bottom portion (31) helps to complete an electrically conductive path through the substrate.

公开(公告)号：EP0969707A2

公开(公告)日：2000-01-05

申请号：EP99201699.8

申请日：1999-05-28

Applicant: Matsushita Electric Works, Ltd.

Inventor： Yoshioka, Hirokazu ,  Yoshida, Norio ,  Tanaka, Kenichiro

IPC: H05K3/46 ,  H05K3/00

CPC classification number: H05K3/4652 ,  H05K1/116 ,  H05K3/0035 ,  H05K3/0044 ,  H05K3/0055 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/0969 ,  H05K2201/098 ,  H05K2201/09863 ,  H05K2203/025 ,  H05K2203/0554 ,  H05K2203/0796 ,  H05K2203/095 ,  H05K2203/1383 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/4916 ,  Y10T29/49165

Abstract: A multilayer printed wiring board is formed with a plurality of conductor layers laminated as a whole with insulating layers interposed, a non-penetrating via hole provided in the insulating layer as bottomed by the conductor layer exposed, a plated layer provided inside the via hole for electric connection between the conductor layers, the via hole being formed to be of a concave curved surface of a radius in a range of 20 to 100 µm in axially sectioned view at continuing zone of inner periphery to bottom surface of the via hole, whereby the equipotential surfaces occurring upon plating the plated layer are curved along the continuing zone to unify the density of current for rendering the plated layer uniform in the thickness without being thinned at the continuing zone.

Abstract translation: 多层印刷线路板由多个导体层整体层叠而形成，绝缘层介于其间，设置在绝缘层中的非贯通通孔，所述绝缘层由于暴露的导体层而有底，设置在通孔内用于 所述导体层之间的电连接在所述通孔的内周到底面的连续区处沿所述轴向剖视图形成为具有在20至100μm范围内的半径的凹曲面， 在电镀镀层时发生的等势表面沿着连续区域弯曲，以统一电流密度，以使电镀层在厚​​度上均匀，而不在连续区域变薄。

公开(公告)号：EP0805614A1

公开(公告)日：1997-11-05

申请号：EP96938496.5

申请日：1996-11-18

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： SASAOKA, Kenji ,  ODAIRA, Hiroshi ,  FUJIWARA, Madoka ,  IKEGAYA, Fumitoshi ,  MORI, Takahiro

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/46 ,  H01L23/48

CPC classification number: H01L24/16 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/17 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/351 ,  H05K1/095 ,  H05K1/116 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09454 ,  H05K2201/0969 ,  H05K2201/09863 ,  H05K2203/1189 ,  H05K2203/1572 ,  Y10S428/901 ,  Y10T428/24917 ,  H01L2924/00

Abstract: A multilayered wiring board using conductive pillars for the interconnection of wiring layers. Since through holes are bored in the via lands of the wiring layers of the multilayered wiring board, the stress applied between the conductive pillars and wiring layers can be released at the time of connecting the conducive pillars to the via lands. Since the external side face of each conductive pillar smoothly continues to the surface of the via land at the contact section between the conductive pillar and the via land, the notch effect is relieved. Therefore, the reliability of the interconnection is secured even when a stress is applied to the connections during the manufacturing of the multilayered wiring board, and the mounting of electronic parts, etc.

Abstract translation: 使用导电支柱的布线层的布线的多层布线板。 由于通孔在通过该多层布线板的布线层的焊盘钻孔，所施加的导电柱和配线层之间的应力可以在通孔连接盘连接利于柱的时间被释放。 由于每个导电柱的外侧面平滑地继续的经由国家在导电柱和经由陆地之间的接触部分的表面上，缺口效应被减轻。 因此，互连的可靠性，即使当固定的应力的制造多层布线板的过程中施加于连接，并且电子部件的安装等