公开(公告)号：EP1705973A3

公开(公告)日：2009-01-21

申请号：EP06014607.3

申请日：1996-10-23

Applicant: IBIDEN CO., LTD.

Inventor： Kawamura, Yoichiro ,  Murase, Hideki ,  Asai, Motoo

IPC: H05K3/46 ,  H05K3/38

CPC classification number: H05K3/0094 ,  H05K3/382 ,  H05K3/384 ,  H05K3/4602 ,  H05K2201/0129 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2203/0773

Abstract: A build-up multilayer printed circuit board in which an interlaminar insulating layer (2) and a conductor layer (5, 5') are alternately laminated on at least one surface of a wiring substrate (1) having a conductor circuit and a through-hole (9), and the conductor layers (5, 5') are electrically connected to each other through a viahole (7) formed in the interlaminar insulating layer (2), characterized in that a roughened layer (11) is formed on the surface of the conductor in an inner wall of the through-hole (9), and a resin filler comprising a resin and inorganic particles is filled in the through-hole (9) formed in the substrate (1).

Abstract translation: 一种在具有导体电路（4）和通孔（9）的布线基板（1）的表面上交替层叠层间绝缘层和导体层的积层多层印刷电路板，并且导体 层通过形成在层间绝缘层中的通孔彼此电连接，其特征在于，在所述通孔（9）的内壁的导体表面上形成有粗糙层（11）和树脂填料（ 10）填充在形成在布线基板（1）中的通孔（9）中。

公开(公告)号：EP2006909A2

公开(公告)日：2008-12-24

申请号：EP07745152.4

申请日：2007-06-13

Applicant: Panasonic Corporation

Inventor： TSUMURA, Tetsuya Panasonic Corporation ,  NISHIYAMA, Hiroharu Panasonic Corporation ,  TSUJIMOTO, Etsuo Panasonic Corporation

IPC: H01L23/36 ,  H01L23/12 ,  H05K1/02 ,  H05K3/06 ,  H05K3/08

CPC classification number: H05K3/202 ,  H01L23/3737 ,  H01L23/49861 ,  H01L24/81 ,  H01L2924/12042 ,  H01L2924/15747 ,  H05K1/0373 ,  H05K1/056 ,  H05K3/027 ,  H05K3/06 ,  H05K2201/0209 ,  H05K2201/0376 ,  H05K2201/09118 ,  H05K2201/098 ,  H05K2201/09881 ,  H05K2201/10106 ,  H05K2203/0369 ,  H05K2203/1476 ,  H01L2924/00

Abstract: A heat dissipating wiring board comprises: a metal wiring plate with a circuit pattern formed therein: a filler containing resin layer embedded with the metal wiring plate such that a top surface of the metal wiring plate is exposed; and a heat dissipating plate arranged on an under surface of the filler containing resin layer, wherein the circuit pattern is formed of a through groove provided in the metal wiring plate, and this through groove is made up of: a fine groove that opens at the top surface of the metal wiring plate; and an expanded groove that expands from a lower end of the fine groove toward the under surface of the metal wiring plate. The heat dissipating wiring board is capable of improving reliability against electric insulation due to a dust or the like in a space of the through groove.

Abstract translation: 散热布线板包括：金属布线板，其中形成有电路图案;埋入金属布线板的填料容纳树脂层，使金属布线板的上表面露出; 以及布置在所述填料容纳树脂层的下表面上的散热板，其中所述电路图案由设置在所述金属布线板中的通孔形成，并且所述通孔由以下部分构成：细槽 金属布线板顶表面; 以及从所述细槽的下端向所述金属配线板的下表面扩展的扩径槽。 散热布线板能够提高通过贯通槽的空间中的灰尘等的电绝缘性的可靠性。

公开(公告)号：EP1445996B1

公开(公告)日：2008-08-20

申请号：EP04011285.6

申请日：1996-10-23

Applicant: IBIDEN CO., LTD.

Inventor： Kawamura, Yoichiro ,  Murase, Hideki ,  Asai, Motoo

IPC: H05K3/46

CPC classification number: H05K3/0094 ,  H05K3/382 ,  H05K3/384 ,  H05K3/4602 ,  H05K2201/0129 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2203/0773

公开(公告)号：EP1954112A1

公开(公告)日：2008-08-06

申请号：EP06822580.4

申请日：2006-10-30

Applicant: Sumitomo Bakelite Company, Ltd.

Inventor： KONDO, Masayoshi c/o Akita Sumitomo Bake Co. Ltd.

IPC: H05K3/46

CPC classification number: H05K3/4673 ,  H05K3/386 ,  H05K3/4617 ,  H05K3/4626 ,  H05K3/4647 ,  H05K2201/09881 ,  H05K2203/0264 ,  H05K2203/066 ,  H05K2203/1189

Abstract: A method for fabricating a multilayer circuit board, including: preparing a film 1 with interlayer adhesive in which a first protective film 102 and a first interlayer adhesive 104 are stacked; preparing a first circuit board 2 having a first base 202 and a conductive post 204 protruding from the first base 202; stacking the surface of the first interlayer adhesive and the surface including the conductive post together; peeling off the first protective film 102; preparing a second circuit board 3 including a conductive pad 302 receiving the conductive post 204; and stacking and bonding the first circuit board 2 and the second circuit board 3 through the first interlayer adhesive 104 so that the conductive post 204 and the conductive pad 302 face each other, wherein in the peeling off, the first interlayer adhesive 104 at the top portion 206 of the conductive post is selectively removed while peeling off the first protective film 102.

Abstract translation: 一种制造多层电路板的方法，包括：准备膜1与其中的第一保护膜102和第一层间粘合剂片104层叠层间粘合剂; 制备具有第一基座202和导电柱204从第一基部202突出的第一电路基板2; 堆叠所述第一层间粘合剂的表面和该表面包括所述后导电在一起; 剥离所述第一保护膜102; 制备第二电路板3包括：接收导电柱204的导电焊盘302; 和堆叠并通过第一层间粘合剂104的第一电路板2和第二电路板3接合，从而DASS死导电柱204和导电焊盘302彼此面对，worin在剥落，在顶部的第一层间粘合剂104 导电柱的部分206可有选择地同时剥离所述第一保护膜除去第102

公开(公告)号：EP1632797B1

公开(公告)日：2007-11-14

申请号：EP05025821.9

申请日：2000-09-13

Applicant: Kabushiki Kaisha Toshiba

Inventor： Hiraoka, Toshiro ,  Asakawa, Koji ,  Hotta, Yasuyuki

IPC: G02B6/12 ,  H01L23/498 ,  H05K3/46

CPC classification number: H05K3/4614 ,  B82Y20/00 ,  G02B6/1225 ,  G03F7/0002 ,  H01L2924/0002 ,  H01P1/2005 ,  H05K1/0306 ,  H05K1/0313 ,  H05K3/107 ,  H05K3/185 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/46 ,  H05K2201/0116 ,  H05K2201/0376 ,  H05K2201/09881 ,  H05K2201/10378 ,  Y10T29/49126 ,  H01L2924/00

公开(公告)号：EP0923094B1

公开(公告)日：2006-09-20

申请号：EP98122945.3

申请日：1998-12-03

Applicant: TDK Corporation

Inventor： Tokuoka, Yasumichi ,  Nomura, Takeshi

IPC: H01G4/30

CPC classification number: H05K3/4667 ,  H01G4/30 ,  H01G4/308 ,  H05K1/0306 ,  H05K3/046 ,  H05K2201/09881 ,  H05K2203/0108 ,  H05K2203/0528 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49126 ,  Y10T29/49128

公开(公告)号：EP1677585A1

公开(公告)日：2006-07-05

申请号：EP05704388.7

申请日：2005-01-28

Applicant: IBIDEN CO., LTD.

Inventor： KARIYA, Takashi ,  FURUTANI, Toshiki

IPC: H05K3/46

CPC classification number: H01L24/16 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K1/0271 ,  H05K1/0373 ,  H05K1/111 ,  H05K1/115 ,  H05K3/243 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/068 ,  H05K2201/09881 ,  H05K2201/10674 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49204 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A multilayer printed wiring board 10 includes: a core substrate 20; a build-up layer 30 formed on the core substrate 20 and having a conductor pattern 32 on an upper surface; a low elastic modulus layer 40 formed on the build-up layer 30; lands 52 that are disposed on an upper surface of the low elastic modulus layer 40 and connected via solder bumps 66 to a semiconductor chip 70; and conductor posts 50 that are passing through the low elastic modulus layer 40 and electrically connecting lands 52 with conductor patterns 32. The conductor posts 50 are formed to have the diameters of an upper portion and a lower portion of 80µm, the diameter of an intermediate portion of 35µm, the height of 200µm, and the aspect ratio Rasp (height/minimum diameter) of 5.7 and the maximum diameter/minimum diameter of 2.3.

Abstract translation: 多层印刷线路板10包括：芯基板20; 形成在芯基板20上并且在上表面上具有导体图案32的堆积层30; 形成在积层30上的低弹性模量层40; 焊盘52设置在低弹性模量层40的上表面上并通过焊锡凸块66连接到半导体芯片70; 以及导体柱50，其穿过低弹性模量层40和电连接焊盘52与导体图案32.导体柱50形成为具有80μm的上部和下部的直径，中间部分的直径 35μm，高度200μm，纵横比Rasp（高/最小直径）为5.7，最大直径/最小直径为2.3。

公开(公告)号：EP1626420A2

公开(公告)日：2006-02-15

申请号：EP05017300.4

申请日：2005-08-09

Applicant: TDK Corporation

Inventor： Abe, Kyotaro ,  Ishiyama, Tamotsu ,  Sato, Shigeki

IPC: H01G4/30

CPC classification number: C04B35/6342 ,  C04B35/4682 ,  C04B35/6261 ,  C04B35/62625 ,  C04B35/6263 ,  C04B35/6264 ,  C04B35/62665 ,  C04B35/632 ,  C04B35/64 ,  C04B2235/3206 ,  C04B2235/3215 ,  C04B2235/3225 ,  C04B2235/3239 ,  C04B2235/3262 ,  C04B2235/3436 ,  C04B2235/3454 ,  C04B2235/5445 ,  C04B2235/6025 ,  C04B2235/6582 ,  C04B2235/663 ,  H01G4/308 ,  H05K1/0306 ,  H05K3/207 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/09881 ,  H05K2203/0156 ,  Y10T428/252

Abstract: A release layer paste used for producing a multilayer electronic device, used in combination with an electrode layer paste including terpineol, dehydroterpineol, terpineol acetate, or dehydroterpineol acetate and including a ceramic powder, organic vehicle, plasticizer, and dispersion agent, the organic vehicle containing a binder having polyvinyl acetal as its main ingredient, a ratio (P/B) of the ceramic powder and the binder and plasticizer being controlled to 1.33 to 5.56 (however, excluding 5.56).

Abstract translation: 用于制造叠层型电子部件，组合使用，萜品醇乙酸酯对电极层用糊料包括萜品醇，dehydroterpineol或乙dehydroterpineol和包含陶瓷粉末，有机载体，增塑剂和分散剂A剥离层用糊料，有机载体含 具有粘合剂的聚乙烯醇缩醛为主要成分，所述陶瓷粉末的比（P / B）和粘合剂和增塑剂被控制到1点33分至5点56分（但是，不包括5点56分）。

公开(公告)号：EP1314172B8

公开(公告)日：2005-06-15

申请号：EP01960431.3

申请日：2001-06-30

Applicant: Moeller GmbH

Inventor： SCHMITZ, Gerd

IPC: H01C17/065

CPC classification number: H05K1/167 ,  H01C17/0652 ,  H05K1/0257 ,  H05K1/095 ,  H05K3/386 ,  H05K2201/0323 ,  H05K2201/09881 ,  H05K2203/1453 ,  Y10T29/49099

Abstract: The invention relates to an electronic assembly, in particular, for low power consumption electric switching devices such as low power contactors, time relays or the like. In order to provide protection against input current pulses, an ohmic resistor (6) is provided in the form of a resistive layer that is applied by pressing.

公开(公告)号：EP1471167A3

公开(公告)日：2005-02-02

申请号：EP04252270.6

申请日：2004-04-16

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Murayama, Kei Shinko Electric Industries Co., Ltd.

IPC: C23C18/16 ,  C23C18/28

CPC classification number: H05K3/244 ,  C23C18/1605 ,  C23C18/1608 ,  C23C18/1635 ,  C23C18/1651 ,  C23C18/1889 ,  C23C18/208 ,  C23C18/285 ,  C23C18/30 ,  C23C18/36 ,  H05K2201/0761 ,  H05K2201/09881 ,  H05K2203/013 ,  H05K2203/0716 ,  H05K2203/072 ,  H05K2203/0796

Abstract: An electroless plating method of the present invention includes the steps of preparing a substrate (15) having an insulating body (10) and a conductive pattern (12) formed thereon, adhering a catalytic metal (14) serving as a catalyst of an electroless plating onto the insulating body (10) and the conductive pattern (12), forming selectively a protection film (16) or an oxidizing agent used to oxidize the catalytic metal on the catalytic metal (14) in a space portion (S) between the conductive pattern (12), and forming selectively a metal layer (18) on the conductive pattern (12) by the electroless plating.