公开(公告)号：EP2091311B1

公开(公告)日：2013-03-06

申请号：EP07831157.8

申请日：2007-11-02

Applicant: IBIDEN CO., LTD.

Inventor： YOSHIKAWA, Kazuhiro

IPC: H05K3/46 ,  H05K1/16

CPC classification number: H05K1/162 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/113 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09309 ,  H05K2201/09718 ,  H05K2201/10515 ,  H05K2201/10712

公开(公告)号：EP2449863A1

公开(公告)日：2012-05-09

申请号：EP10732837.9

申请日：2010-06-25

Applicant: AT & S Austria Technologie & Systemtechnik Aktiengesellschaft

Inventor： FROSCH, Ronald ,  RIEDLER, Manfred

IPC: H05K1/02

CPC classification number: H05K1/02 ,  H05K1/0298 ,  H05K1/0373 ,  H05K3/3452 ,  H05K2201/012 ,  H05K2201/0209 ,  H05K2201/09309 ,  H05K2201/0989

Abstract: In the case of a multilayered printed circuit board (20), more particularly a flame‑resistant and/or smoke‑suppressing multilayered printed circuit board, consisting of a plurality of interconnected layers (2, 3, 12, 13) composed of incombustible, conductive material and layers (1, 11) composed of non‑conductive material, two layers (2, 3, 12) composed of a conductive material in each case being separated by at least one layer (1, 11) composed of a non‑conductive material, it is provided that the printed circuit board (20) contains in its interior at least two layers (2, 3, 12) having a surface proportion of at least 50%, more particularly at least 70%, composed of the incombustible, conductive material, as a result of which a multilayered printed circuit board (20) having improved flame resistance and reduced smoke evolution can be made available.

公开(公告)号：EP2259669A4

公开(公告)日：2011-12-28

申请号：EP09725467

申请日：2009-03-24

Applicant: NGK SPARK PLUG CO

Inventor： MURAMATSU MASAKI

IPC: H05K3/46 ,  H01L23/12

CPC classification number: H05K1/162 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1461 ,  H01L2924/15311 ,  H05K1/02 ,  H05K1/0231 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09309 ,  H05K2201/096 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00

Abstract: An objective is to provide a component-incorporated wiring substrate capable of solving a problem caused by an increase in length of wiring lines that connect a component and a capacitor. A component-incorporated wiring substrate 10 includes a core substrate 11, a first capacitor 301, a wiring laminate portion 31, and a second capacitor 101. An accommodation hole portion 90 of the core substrate 11 accommodates the first capacitor 101 therein, and a component-mounting region 20 is set on a surface 39 of the wiring laminate portion 31. The second capacitor 101 has electrode layers 102, 103 and a dielectric layer 104. The second capacitor 101 is embedded in the wiring laminate portion 31 in such a state that first main surfaces 105, 107 and second main surfaces 106, 108 are in parallel with the surface 39 of the wiring laminate portion 31, and is disposed between the first capacitor 301 and the component-mounting region 20.

公开(公告)号：EP2346310A3

公开(公告)日：2011-10-05

申请号：EP11161217.2

申请日：2002-09-26

Applicant: FUJITSU LIMITED

Inventor： Kusagaya, Toshihiro ,  Yoneda, Yasuhiro ,  Mizutani, Daisuke ,  Iijima, Kazuhiko ,  Suwa, Yuji

IPC: H05K3/46 ,  H05K1/02

CPC classification number: H05K3/4641 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/01087 ,  H05K1/0216 ,  H05K1/113 ,  H05K3/0035 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K3/4688 ,  H05K2201/0129 ,  H05K2201/0154 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/1394

Abstract: An organic multilayer wiring circuit board comprises: a signal layer (L4); a first insulating layer (24) made of resin and arranged on the signal layer (L4); a lamination body arranged on the first insulating layer (24), which lamination body includes: an electric power source layer (L3); a ground layer (L2); and a second insulating layer (16) made of polyimide and provided between the electric power source layer (L3) and the ground layer (L2); the second insulating layer (16) having a thickness of 4 to 25µm and a thermoplastic adhesive property on both faces thereof; a third insulating layer (14) made of resin and arranged on the lamination body; and an uppermost conductive layer (L1) arranged on the third insulating layer (14), on which an electronic component is to be mounted.

Abstract translation: 提供一种廉价的多层布线电路板，其能够通过减小电路的电感来抑制高频噪声的产生，从而在电路上进行高频开关操作。 多层布线电路板包括：被指定为第一层（L1）的最上层，其上安装有部件; 布置有接地层和电源层中的一个的第二层（L2）; 第三层（L3），另一层布置在其上; 以及布置在接地层和电源层之间的绝缘层（16）。 作为在电源层和接地层之间配置的绝缘层（16）的材料，使用两面具有热塑性粘合性的树脂层。

公开(公告)号：EP2141971A4

公开(公告)日：2011-01-05

申请号：EP07829842

申请日：2007-10-15

Applicant: IBIDEN CO LTD

Inventor： TANAKA HIRONORI ,  SHIMIZU KEISUKE

IPC: H05K3/46 ,  H05K1/16

CPC classification number: H05K1/162 ,  H05K1/09 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09718 ,  Y10T29/4913

公开(公告)号：EP2232965A2

公开(公告)日：2010-09-29

申请号：EP08870919.1

申请日：2008-12-10

Applicant: PPG Industries Ohio, Inc.

Inventor： WANG, Alan E. ,  OLSON, Kevin C. ,  PAWLIK, Michael J.

IPC: H05K3/42 ,  H05K1/05

CPC classification number: H05K3/429 ,  H01L2924/0002 ,  H05K3/445 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2203/135 ,  Y10T29/49126 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A process for fabricating a circuit board includes: providing a substrate (10) including a first electrically conductive core (12) having a first insulating coating (14) on a first side and a second insulating coating (16) on a second side, forming an opening (22) in the first and second insulating coatings and the first electrically conductive core, exposing an edge (24) of the conductive core within the opening, and electrodepositing a third insulating material (28) on the exposed edge of the first electrically conductive core. A circuit board fabricated using the process is also provided.

公开(公告)号：EP1777745A3

公开(公告)日：2010-05-05

申请号：EP06019654.0

申请日：2006-09-20

Applicant: E.I. DU PONT DE NEMOURS AND COMPANY

Inventor： Borland, William J. ,  Ferguson, Saul

IPC: H05K1/16 ,  H01L23/50 ,  H01L23/498

CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/113 ,  H05K1/162 ,  H05K2201/09309 ,  H05K2201/09763 ,  H05K2201/10734

Abstract: A device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor (240) wherein said embedded singulated capacitor comprises at least a first electrode and a second electrode and wherein said embedded singulated capacitor is positioned on the outer layer of the power core with both first and second electrodes of the capacitor on the outer layer of the power core so that at least one Vcc (power) terminal and at least one Vss (ground) terminal of a semiconductor device (201) can be directly connected to at least one first and at least one second electrode, respectively.

公开(公告)号：EP2160931A1

公开(公告)日：2010-03-10

申请号：EP08765405.9

申请日：2008-06-04

Applicant: Canon Kabushiki Kaisha

Inventor： HAYASHI, Seiji

IPC: H05K1/02

CPC classification number: H05K1/0231 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2924/15311 ,  H01L2924/19105 ,  H05K1/0233 ,  H05K1/0234 ,  H05K1/0298 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09781 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00014

Abstract: A power source terminal and a ground terminal for a semiconductor integrated circuit are connected to a conductor pattern through a capacitor. The conductor pattern is connected, through a filter, to a plane conductor connected to neither a ground plane nor a power source plane. Thus, a common mode noise arising from between the power source and the ground is caused to flow into the plane conductor. This reduces the common mode noise flowing in the ground and the power source of the printed wiring board, which relatively act as antennas.

Abstract translation: 电源端子和半导体集成电路的接地端子通过电容器连接到导体图案。 导体图案通过滤波器连接到不与接地层和电源平面连接的平面导体。 因此，引起从电源和地之间产生的共模噪声流入平面导体。 这降低了相对地作为天线的在地面和印刷电路板的电源中流动的共模噪声。

公开(公告)号：EP2156716A1

公开(公告)日：2010-02-24

申请号：EP08755104.0

申请日：2008-05-07

Applicant: 3M Innovative Properties Company

Inventor： AELING, Ellen, O. ,  MEIS, Michael A. ,  JACKSON, Byron M. ,  DAVID, John, R.

IPC: H05K3/46

CPC classification number: H05K3/4638 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/0393 ,  H05K1/189 ,  H05K3/0097 ,  H05K3/202 ,  H05K3/303 ,  H05K3/386 ,  H05K3/4635 ,  H05K2201/0355 ,  H05K2201/09063 ,  H05K2201/09309 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2201/10106 ,  H05K2203/063 ,  H05K2203/1545 ,  H05K2203/166 ,  Y10T29/4913

Abstract: The present application is directed to a method of producing a multilayer circuit. The method comprises providing a first electrically insulating layer comprising apertures through the layer and bonding the first electrically insulating layer with a first conductive layer. The first conductive layer is bonded to the first electrically insulating layer in register to the apertures in the electrically insulating layer and the multilayer circuit is produced at a sustained rate. In another embodiment, the method comprises providing a second electrically insulating layer and bonding the second electrically insulating layer with the first conductive layer opposite the first electrically insulating layer.

公开(公告)号：EP2141971A1

公开(公告)日：2010-01-06

申请号：EP07829842.9

申请日：2007-10-15

Applicant: Ibiden Co., Ltd.

Inventor： TANAKA, Hironori ,  SHIMIZU, Keisuke

IPC: H05K3/46

CPC classification number: H05K1/162 ,  H05K1/09 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09718 ,  Y10T29/4913

Abstract: Multilayer printed wiring board (10) comprises core substrate (20), insulation layer (26) on the core substrate laminated on core substrate (20) and capacitor section (40) formed on the insulation layer (26) on the core substrate. Capacitor section (40) is structured by sandwiching high dielectric layer (43) with lower electrode (41) that accumulates negative charges and upper electrode (42) that accumulates positive charges. The ionization tendency of a metal to form lower electrode (41) is larger than that of a metal to form upper electrode (42). For example, a metal to form lower electrode (41) is nickel and a metal to form upper electrode (42) is copper.

Abstract translation: 多层印刷线路板10包括核心基板20，层压在核心基板20上的核心基板上的绝缘层26和形成在核心基板上的绝缘层26上的电容器部分40。 电容器部40通过在高介电层43中夹持积蓄负电荷的下部电极41和积蓄正电荷的上部电极42而构成。 形成下部电极（41）的金属的电离倾向大于形成上部电极（42）的金属的离子化倾向。 例如，形成下部电极（41）的金属是镍，形成上部电极（42）的金属是铜。