公开(公告)号：EP1621054A1

公开(公告)日：2006-02-01

申请号：EP04728728.9

申请日：2004-04-21

Applicant: Senseair AB

Inventor： MARTIN, Hans Göran Evald ,  HJORT, Klas Anders ,  LINDBERG, Mikael Peter Erik

IPC: H05K3/18

CPC classification number: H05K3/0041 ,  G01K2211/00 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/002 ,  H05K2201/09609 ,  H05K2201/0979 ,  H05K2203/092 ,  H01L2924/00

Abstract: The present invention comprises a processed thin film substrate (10) and a method therefore, in order to produce a flexible printed circuit card, having a plurality of microvias going or passing through the thin film substrate and electrically connected along faced-away surfaces, in order to form an electric circuit. A first a number of real nano-tracks are filled with a first material (M1), having good electric properties, for the formation of a first number of, here denominated, first vias (V10, V30, V50), that a second number of real nano-tracks are filled with a second material (M2), having good electric properties, for the formation of a second number of, here denominated, second vias (V20, V40, V60). The first material (M1) and the second material (M2) of said first and second vias (V10-V60) are chosen having mutually different thermoelectric properties. A material surface-applied to the thin film substrate, coated on both sides (10a, 10b) of the thin film substrate (10), is distributed and/or adapted in order to allow the electrical interconnection of first vias, allocated the first material (M1), with second vias, allocated the second material (M2), and that a first via (V10) included in a series connection and a last via (V60) included in the series connection are serially co-ordinated in order to form an electric thermocouple (100) or other circuit arrangement.

公开(公告)号：EP1030366B1

公开(公告)日：2005-10-19

申请号：EP00102116.1

申请日：2000-02-04

Applicant: MITSUBISHI GAS CHEMICAL COMPANY, INC.

Inventor： Kimbara, Hidenori, Mitsubishi Gas Chem. Co., Inc. ,  Ikeguchi, Nobuyuki, Mitsubishi Gas Chem. Co., Inc. ,  Komatsu, Katsuji, Mitsubishi Gas Chem. Co., Inc.

IPC: H01L23/32 ,  H01L23/498

CPC classification number: H01L24/45 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/01105 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/40252 ,  H05K1/0373 ,  H05K1/112 ,  H05K3/0038 ,  H05K3/3436 ,  H05K3/4629 ,  H05K2201/0209 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/0979 ,  Y02P70/613 ,  Y10T428/24917 ,  Y10T428/31681 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0002 ,  H01L2224/45099 ,  H01L2224/43

Abstract: Provided is a printed wiring board for a chip size scale package, which overcomes the poor adhesion of solder balls to a base material which poor adhesion is caused by a recent decrease in the size of the solder balls, and in the chip size scale package, the distortion of the printed wiring board is decreased and the distortion of a semiconductor plastic package formed by mounting a semiconductor chip on the printed wiring board by wire bonding or flip chip bonding is decreased. The printed wiring board has, as a substrate for a chip scale package, a double-side copper-clad laminate formed of an insulation layer and having copper foils on both surfaces, wherein the double-side copper-clad laminate has an upper copper foil surface and a lower copper foil surface, the upper copper foil surface has a wire bonding or flip chip bonding terminal and has a copper pad in a position where the copper pad can be electrically connected to said wire bonding or flip chip bonding terminal and can be connected to a blind via hole formed in the lower copper surface, the lower copper foil surface has a solder-balls-fixing pad in a position corresponding to said copper pad, the solder-balls-fixing pad has at least 2 blind via holes within itself, and the solder-balls-fixing pad connected to a reverse surface of the copper pad with a conductive material is electrically connected with solder balls which are melted and filled in blind via holes so as to be mounded.

公开(公告)号：EP1329990B1

公开(公告)日：2005-10-12

申请号：EP03000591.2

申请日：2003-01-14

Applicant: YAZAKI CORPORATION

Inventor： Tanaka, Yoshiyuki ,  Ashiya, Hiroyuki ,  Maki, Yayoi

IPC: H01R9/24 ,  B60R16/02

CPC classification number: B60R16/0238 ,  H01R9/2466 ,  H05K3/301 ,  H05K3/306 ,  H05K3/308 ,  H05K3/3447 ,  H05K2201/0979 ,  H05K2201/10424 ,  H05K2201/10651 ,  H05K2201/10757 ,  H05K2201/10856 ,  H05K2201/2036 ,  Y10S439/949

公开(公告)号：EP1565047A1

公开(公告)日：2005-08-17

申请号：EP05075212.0

申请日：2005-01-27

Applicant: Delphi Technologies, Inc.

Inventor： Post, Scott E. ,  Cheok, Cheng Gek, c/o 700 Lorong 1-Toa Payoh ,  Stillabower, Morris D. ,  Nah, Chih Kai ,  Mandel, Larry M. ,  Yong, Sim Ying

IPC: H05K3/34

CPC classification number: H05K1/112 ,  H05K3/3442 ,  H05K2201/09572 ,  H05K2201/0979 ,  H05K2201/10636 ,  H05K2203/0455 ,  Y02P70/611 ,  Y02P70/613

Abstract: An electronic package (10) is provided having a surface mount electronic device (40) connected to a circuit board (12). The package (10) includes a circuit board (12) and a surface mount electronic device (40). A mounting pad (28) is formed on the circuit board (12). A plurality of vias (30) are formed each having an opening extending into the circuit board (12) and extending through the mounting pad (28). The package (10) further includes a solder joint (32) connecting a contact terminal (42) of the surface mount device (40) to the mounting pad (28) on the circuit board (12). The solder joint (32) extends at least partially into the openings in each of the plurality of vias (30) to support the arrangement of the surface mount device (40) on the circuit board (12).

Abstract translation: 提供具有连接到电路板（12）的表面安装电子装置（40）的电子封装（10）。 封装（10）包括电路板（12）和表面贴装电子器件（40）。 在电路板（12）上形成安装垫（28）。 形成多个通孔（30），每个通孔具有延伸到电路板（12）中并延伸穿过安装垫（28）的开口。 封装（10）还包括将表面安装器件（40）的接触端子（42）连接到电路板（12）上的安装焊盘（28）的焊接接头（32）。 焊接接头（32）至少部分地延伸到多个通孔（30）中的每一个中的开口中，以支撑表面安装器件（40）在电路板（12）上的布置。

公开(公告)号：EP1563573A2

公开(公告)日：2005-08-17

申请号：EP03790027.1

申请日：2003-11-18

Applicant: THE SIEMON COMPANY

Inventor： CELELLA, Brian ,  PAGLIARULO, Vito ,  MULLIN, Daniel

IPC: H01R12/04

CPC classification number: H05K1/0248 ,  H05K1/0228 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/09781 ,  H05K2201/0979 ,  H05K2201/10189

Abstract: A printed circuit board (16) providing crossatalk compensation. The printed circuit board includes first plated through holes (41-48) for receiving a first connecting component and second plated through holes (51-58) for receiving a second connecting component. A signal carrying trace transmits a signal from one of the first plated through hole to one of the second plated through holes. A phase delay control trace (60) is in electrical connection with one of the first plated through holes. The phase delay control trace (60) affects phase delay of the signal from the one of the first plated through holes to the one of the second plated through holes.

Abstract translation: 提供交叉阻滞补偿的印刷电路板（16）。 印刷电路板包括用于接收第一连接部件的第一电镀通孔（41-48）和用于接收第二连接部件的第二电镀通孔（51-58）。 信号承载迹线将来自第一电镀通孔中的一个的信号传输至第二电镀通孔中的一个。 相位延迟控制轨迹（60）与第一电镀通孔中的一个电连接。 相位延迟控制迹线（60）影响从第一电镀通孔之一到第二电镀通孔之一的信号的相位延迟。

公开(公告)号：EP1206170B1

公开(公告)日：2005-06-08

申请号：EP01912339.7

申请日：2001-03-14

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： SUETSUGU, Kenichiro ,  KOSHI, Masuo ,  TODOROKI, Kenichiro ,  HIBINO, Shunji ,  TAKANO, Hiroaki ,  NAKATA, Mikiya ,  MAEDA, Yukio

IPC: H05K1/18 ,  H05K3/34 ,  H05K1/11

CPC classification number: H05K3/3447 ,  H05K1/0293 ,  H05K1/115 ,  H05K1/116 ,  H05K3/3452 ,  H05K3/3463 ,  H05K3/4092 ,  H05K2201/0373 ,  H05K2201/0397 ,  H05K2201/09663 ,  H05K2201/0979 ,  H05K2201/099

Abstract: A bonded structure comprising a board provided with a through hole, a land disposed on the periphery of the through hole, and a lead led out from an electronic part and placed in the through hole. The land comprises an wall face land part on the wall face of the through hole, and front and rear surface land parts on the front and rear surfaces of the board. A fillet for connecting the land with the lead comprises upper and lower fillets parts touching the front and rear surface land parts, respectively, wherein the contour of the upper fillet is smaller than the contour of the lower fillet but larger than the size of the through hole. When a lead-free solder material is employed, occurrence of liftoff can be reduced effectively as compared with a conventional one.

公开(公告)号：EP1467430A1

公开(公告)日：2004-10-13

申请号：EP04008777.7

申请日：2004-04-13

Applicant: TDK Corporation

Inventor： Shimoda, Hideaki

IPC: H01P5/08

CPC classification number: H05K1/0251 ,  H01P5/08 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/115 ,  H05K2201/09618 ,  H05K2201/0979 ,  H05K2201/09845

Abstract: Since a width of an edge portion of a signal line of a first high frequency transmission line is changed with respect to a width of another portion thereof, a deviation of impedances in a connection portion of the first and second high frequency transmission lines can be suppressed, so that signal reflections occurred in the connection portion can be lowered and a signal passing characteristic is improved.

Abstract translation: 由于第一高频传输线的信号线的边缘部分的宽度相对于其另一部分的宽度而改变，所以可以抑制第一和第二高频传输线的连接部分中的阻抗的偏差 ，使连接部分发生的信号反射降低，信号通过特性提高。

公开(公告)号：EP0868838B1

公开(公告)日：2003-09-17

申请号：EP97929456.8

申请日：1997-07-17

Applicant: BC Components Holdings B.V.

Inventor： DIJKSTRA, Rinse

IPC: H05K7/10 ,  H01G2/06 ,  H05K3/34

CPC classification number: H01G4/228 ,  H01G2/06 ,  H05K3/308 ,  H05K3/3447 ,  H05K2201/094 ,  H05K2201/0979 ,  H05K2201/10651 ,  H05K2201/10856 ,  H05K2201/10863 ,  H05K2201/10878

Abstract: In this application, a description is given of a passive component comprising two electric connections with a plug-in portion for securing and electrically connecting the component to a printed circuit board, for example an electrolytic capacitor. In accordance with the invention, this component is so constructed that both plug-in portions are provided with two pins, with the plug-in portions being so positioned that the four pins do not extend in a flat plane. By virtue of the measure in accordance with the invention, resoldering of such components can be dispensed with. The use of pins whose length and width are different enables the manual installation of the components in accordance with the invention in the correct position to be simplified.

公开(公告)号：EP1219148A1

公开(公告)日：2002-07-03

申请号：EP00951731.9

申请日：2000-08-10

Applicant: Ford Motor Company

Inventor： LI, Delin ,  BAKER, Jay, DeAvis ,  ACHARI, Achyuta ,  NATION, Brenda, Joyce ,  TRUBLOWSKI, John

IPC: H05K1/11 ,  H05K3/36

CPC classification number: H05K3/361 ,  H01R12/62 ,  H05K1/0293 ,  H05K1/117 ,  H05K1/118 ,  H05K3/0052 ,  H05K3/225 ,  H05K2201/053 ,  H05K2201/09127 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/0979 ,  H05K2203/0228 ,  H05K2203/175

Abstract: A repairable flex circuit (1), comprising: a generally flexible, electrically insulative substrate (2) having a first edge (3) thereof, and a plurality of electrically conductive circuit traces (5) arranged on the substrate. Each circuit trace has an end thereof terminating at a first connector element (8) proximate the first edge (3), and at least one second connector element (13) spaced apart from the first connector element, with each of said first and second connector elements being a plated through hole, a plated blind via, or a solder pad.

公开(公告)号：EP1206170A1

公开(公告)日：2002-05-15

申请号：EP01912339.7

申请日：2001-03-14

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： SUETSUGU, Kenichiro ,  KOSHI, Masuo ,  TODOROKI, Kenichiro ,  HIBINO, Shunji ,  TAKANO, Hiroaki ,  NAKATA, Mikiya ,  MAEDA, Yukio

IPC: H05K1/18 ,  H05K3/34 ,  H05K1/11

CPC classification number: H05K3/3447 ,  H05K1/0293 ,  H05K1/115 ,  H05K1/116 ,  H05K3/3452 ,  H05K3/3463 ,  H05K3/4092 ,  H05K2201/0373 ,  H05K2201/0397 ,  H05K2201/09663 ,  H05K2201/0979 ,  H05K2201/099

Abstract: A connection structure of the present invention has a board with a through hole perforating therethrough, a land formed around the through hole, and a lead extending from an electronic component and disposed in the through hole. The land includes a wall surface land portion formed on a wall surface of the through hole, and front and back surface land portions formed on the front and back surfaces of the board respectively. A fillet connecting the land and the lead includes upper and lower fillet portions respectively contacting with the front and back surface land portions. A profile of the upper fillet portion is smaller than that of the lower fillet portion and is not smaller than that of the through hole. Therefore, occurrence of lift-off is effectively reduced while using a lead-free solder material.

Abstract translation: 本发明的连接结构具有贯穿孔的通孔，形成在通孔周围的台面，以及从电子部件延伸设置在通孔中的引线。 所述平台包括形成在所述通孔的壁面上的壁面陆部，以及分别形成在所述板的前后表面上的前后表面接合部。 连接陆地和铅的圆角包括分别与前表面和后表面陆部接触的上下圆角部分。 上圆角部分的轮廓小于下圆角部分的轮廓，并且不小于通孔的轮廓。 因此，在使用无铅焊料的情况下，有效地减少了剥离的发生。