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1.发明公开公开(公告)号：US20240319762A1
公开(公告)日：2024-09-26
申请号：US18731170
申请日：2024-05-31
发明人： Jianhua Liu , Jinghui Zhu , Ning Song , Tianping Wang , Chienkuang Chen , Diwakar Chopperla , Tianxin Wang , Zhenyu Gu , Xiaozhi Lin
摘要： A configurable semiconductor device (“CSD”) is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.
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2.发明公开公开(公告)号：US20240275406A1
公开(公告)日：2024-08-15
申请号：US18438380
申请日：2024-02-09
发明人： Jingxiang Wang , Yue Han , Zheng Wang , Yunjie Fan , Tianping Wang , Niu Li , Qi Zhou
CPC分类号： H03M13/1105 , G11C29/08 , H03M13/611
摘要： A system and method for testing Error Correcting Code (“ECC”) function of Field Programmable Gate Array (“FPGA”) on-chip block random access memory (“BRAM”) includes control modules, at least two BRAMs with ECC function and sequentially connected to form a ring, and parity bit comparison modules corresponding to each BRAM. Each parity bit comparison module is connected to its corresponding BRAM and the next adjacent BRAM. The control module is used to send data read and write test instructions to each BRAM. Each BRAM is used to read test data sequentially, write test data into next adjacent BRAM whenever the test data is read, and send the first parity bit generated during reading to the corresponding parity bit comparison module. Each parity bit comparison module is used to compare the first and second parity bits, where the second parity bit is generated during the writing of test data. The embodiments of the present invention reduce the required test stimuli and the interactions with upper computer ports, which enhances the test efficiency.
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公开(公告)号：US11874792B2
公开(公告)日：2024-01-16
申请号：US17968646
申请日：2022-10-18
IPC分类号： G06F13/42 , G06F1/08 , H03K19/17736 , H03M9/00 , H03M5/04
CPC分类号： G06F13/4291 , G06F1/08 , H03K19/17744 , H03M5/04 , H03M9/00 , G06F2213/0042
摘要： A method for providing a high-speed data communication between a host and field-programmable gate array (“FPGA”) is disclosed. The method, in one embodiment, is capable of identifying a data rate on a bus containing a P-channel and an N-channel operable to transmit signals in accordance with a high-speed Universal Serial Bus (“USB”) protocol. Upon sampling, by a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel, a second input deserializer is used to sample the second two samples of data signals transmitted by the N-channel in accordance with a second clock signal running twice as fast as the data rate of the N-channel with a ninety (90) degree phase shift. The method subsequently forwards the data signals to one or more configurable logic blocks (“LBs”) in FPGA.
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4.发明授权公开(公告)号：US11843377B2
公开(公告)日：2023-12-12
申请号：US17699043
申请日：2022-03-18
发明人： Jinghui Zhu
IPC分类号： H03K19/17728 , H03K19/173
CPC分类号： H03K19/17728 , H03K19/1735 , H03K19/1737
摘要： A programmable integrated circuit (“PIC”) device includes configurable logic blocks (“LBs”), routing connections, and configuration memory for performing user defined programmed logic functions. Each configurable LB, in one example, includes a set of lookup tables (“LUTs”) and associated registers. The LUTs, for example, are configured to generate one or more output signals in accordance with a set of input signals. The registers are arranged so that each register corresponds to one LUT. In one embodiment, a group of registers, instead of assigning to a group of LUTs across multiple configurable LBs, is allocated or configured as embedded signature registers in PSD. For example, a first register which corresponds or physically situated in the vicinity of first LUT can be designated as an embedded signature register for storing a fixed value or signature information for facilitating device or IC identification.
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公开(公告)号：US20230297259A1
公开(公告)日：2023-09-21
申请号：US18203059
申请日：2023-05-30
发明人： Jinghui Zhu , Diwakar Chopperla
IPC分类号： G06F3/06 , G06F9/4401
CPC分类号： G06F3/0632 , G06F9/4403 , G06F3/0679 , G06F3/0604
摘要： A programmable semiconductor system includes a programmable integrated circuit (“PIC”) and storage capable of facilitating a multi-boot with backup default configuration (“MBC”) process. The PIC, in one embodiment, includes configurable logic blocks (“LBs”), routing connections, and a configuration memory for performing logic functions. The storage includes a first and a second memory. While the first memory stores a user configuration data representing user-defined logic functions, the second memory stores a backup default page (“BDP”) containing default configuration data (“DCD”) for programming or booting PIC to its default setting when the user configuration data fails to boot or program PIC. In one aspect, the user configuration data contains the address of the second memory containing DCD.
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6.发明公开公开(公告)号：US20230246646A1
公开(公告)日：2023-08-03
申请号：US18132984
申请日：2023-04-11
发明人： Jinghui Zhu
IPC分类号： H03K19/1776 , H03K19/17724 , H03K19/17736 , G11C13/00 , G11C11/22 , G11C16/10 , G11C11/16
CPC分类号： H03K19/1776 , H03K19/17724 , H03K19/17736 , G11C13/0069 , G11C13/0004 , G11C11/2275 , G11C16/10 , G11C11/1675
摘要： A programmable integrated circuit device able to be selectively programmed to perform one or more logic functions includes multiple configurable logic blocks (“LBs”), routing fabric, and a nonvolatile memory (“NVM”). While the configurable LBs are able to be selectively programmed to perform one or more logic functions, the routing fabric selectively routes information between the configurable LBs and input/output ports based on a routing configuration signals. The NVM, such as magnetoresistive random access memory (“MRAM”), phase-change memory, or ferroelectric RAM (“FeRAM”), is flexibly organized to contain a configuration NVM storage and a user NVM storage, wherein the user NVM storage is a word addressable memory capable of facilitating random memory access.
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公开(公告)号：US20230103119A1
公开(公告)日：2023-03-30
申请号：US17489749
申请日：2021-09-29
摘要： An automatic measuring system containing configurable integrated circuits is able to process information via captured images. The automatic measuring system includes a metering instrument, a camera, a recognition module, and a localization module. The metering instrument has at least one display for visually displaying a number and measures the amount of measurable substance or resources (i.e., electricity and water) consumed. The camera captures an image of the number representing at least a portion the amount of measurable substance. The recognition module is operable to generate a value in response to the image and the coordinates wherein the coordinates are used to decode the image via restoring captured image to the original readout counter value. The localization module is removably or remotely coupled to the camera and operable to generate the coordinates in accordance with the image captured by the camera.
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8.发明申请公开(公告)号：US20220393685A1
公开(公告)日：2022-12-08
申请号：US17891154
申请日：2022-08-19
发明人： Grant Thomas Jennings , Jinghui Zhu
IPC分类号： H03K19/17788 , H03K19/1776 , H03K19/17704 , H03K19/17784
摘要： A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.
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9.发明授权公开(公告)号：US11496135B2
公开(公告)日：2022-11-08
申请号：US17325025
申请日：2021-05-19
发明人： Grant Thomas Jennings , Jinghui Zhu
IPC分类号： H03K19/177 , H03K19/17788 , H03K19/1776 , H03K19/17704 , H03K19/17784
摘要： A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.
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10.发明授权公开(公告)号：US11216022B1
公开(公告)日：2022-01-04
申请号：US17023178
申请日：2020-09-16
发明人： Jianhua Liu , Jinghui Zhu , Ning Song , Tianping Wang , Chienkuang Chen , Diwakar Chopperla , Tianxin Wang , Zhenyu Gu , Xiaozhi Lin
IPC分类号： G06F1/06
摘要： A field-programmable gate array (“FPGA”) contains a configurable semiconductor organized in multiple clock regions with a clock fabric for facilitating user-defined logic functions. The clock fabric provides a set of regional clock signals (“RCSs”) generated from a clock source with a high clock signal quality (“CSQ”) for clocking logic blocks in a clock region. Also, a set of neighboring clock signals (“NCSs”) or inter-regional clock signals are generated from a neighboring clock source(s) for clocking logic blocks in two neighboring regions. In addition, the clock fabric is operable to provide secondary clock signals (“SCSs”) generated from the RCSs with a low CSQ for clocking logic blocks with less time-sensitive logic operations.
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