公开(公告)号：US20250107195A1

公开(公告)日：2025-03-27

申请号：US18373466

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Thomas O’BRIEN ,  Anindya DASGUPTA ,  Shengsi LIU ,  Saurabh ACHARYA ,  Charles H. WALLACE ,  Baofu ZHU

IPC: H01L29/40 ,  H01L29/08 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit structures having trench contact flyover structures, and methods of fabricating integrated circuit structures having trench contact flyover structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires or a fin. A gate structure is over the plurality of horizontally stacked nanowires or the fin. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires or the fin. A conductive trench contact structure has a first portion laterally spaced apart from the epitaxial source or drain structure, a second portion vertically over the epitaxial source or drain structure, and a third portion between the first portion and the second portion. A dielectric plug is laterally between the epitaxial source or drain structure and the first portion of the conductive trench contact structure, wherein the third portion of the conductive trench contact structure is vertically over the dielectric plug.

公开(公告)号：US20250107147A1

公开(公告)日：2025-03-27

申请号：US18476248

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Mahmut Sami Kavrik ,  Uygar E. Avci ,  Pratyush P. Buragohain ,  Chelsey Dorow ,  Jack T. Kavalieros ,  Chia-Ching Lin ,  Matthew V. Metz ,  Wouter Mortelmans ,  Carl Hugo Naylor ,  Kevin P. O'Brien ,  Ashish Verma Penumatcha ,  Carly Rogan ,  Rachel A. Steinhardt ,  Tristan A. Tronic ,  Andrey Vyatskikh

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/46 ,  H01L27/092 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66 ,  H01L29/76

Abstract: Hybrid bonding interconnect (HBI) architectures for scalability. Embodiments implement a bonding layer on a semiconductor die that includes a thick oxide layer overlaid with a thin layer of a hermetic material including silicon and at least one of carbon and nitrogen. The conductive bonds of the semiconductor die are placed in the thick oxide layer and exposed at the surface of the hermetic material. Some embodiments implement a non-bonding moisture seal ring (MSR) structure.

公开(公告)号：US20250107112A1

公开(公告)日：2025-03-27

申请号：US18371294

申请日：2023-09-21

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Srinivas PIETAMBARAM ,  Mohammad Mamunur RAHMAN ,  Sashi Shekhar KANDANUR ,  Aleksandar ALEKSOV ,  Tarek A. IBRAHIM ,  Rahul N. MANEPALLI

IPC: H01L23/48 ,  H01L23/498

Abstract: Coaxial magnetic inductor structures useful for semiconductor packaging applications are provided. The coaxial magnetic inductors can be located in semiconductor package cores and the semiconductor package cores can be, for example, comprised of an amorphous solid glass material. Methods of manufacturing a coaxial magnetic inductors in a package substrate core are also provided.

公开(公告)号：US20250107108A1

公开(公告)日：2025-03-27

申请号：US18473421

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Sagar Suthram ,  Wilfred Gomes ,  Tahir Ghani ,  Anand S. Murthy ,  Pushkar Sharad Ranade

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: An IC device may include memory layers bonded to a logic layer with inclination. An angle between a memory layer and the logic layer may be in a range from approximately 0 to approximately 90 degrees. The memory layers may be over the logic layer. The IC device may include one or more additional logic layers that are parallel to a memory layer or perpendicular to a memory layer. The one or more additional logic layers may be over the logic layer. A memory layer may include memory cells. The logic layer may include logic circuits (e.g., sense amplifier, word line driver, etc.) that control the memory cells. Bit lines (or word lines) in different memory layers may be coupled to each other. A bit line and a word line in a memory layer may be controlled by logic circuits in different logic layers.

公开(公告)号：US20250107107A1

公开(公告)日：2025-03-27

申请号：US18471402

申请日：2023-09-21

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Sagar Suthram ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Anand S. Murthy ,  Tahir Ghani

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: An IC device may include memory layers over a logic layer. A memory layer may include memory arrays and one or more peripheral circuits coupled to the memory arrays. A memory array may include memory cells arranged in rows and columns. A row of memory cells may be associated with a word line. A column of memory cells may be associated with a bit line. The logic layer includes one or more logic circuits that can control data read operations and data write operations of the memory layers. The logic layer may also include a power interconnect, which facilitates power delivery to the memory layers, and a signal interconnect, which facilitates signal transmission within the IC device. The IC device may further include vias that couple the memory layers to the logic layer. Each via may be connected to one or more memory layers and the logic layer.

公开(公告)号：US20250107044A1

公开(公告)日：2025-03-27

申请号：US18373537

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Jose Diaz Marin ,  Fabian Garita Gonzalez ,  Jose Andres Santamaria Cordero ,  Ronald Jose Loaiza Baldares ,  Manfred Humberto Hernandez Calderon ,  Ruander Cardenas ,  Sofia Solis Loáiciga

IPC: H05K7/20

Abstract: Cooling provided by a thermal management system may be controlled actively to reduce or prevent entering a dry out state. The systems and methods described herein include monitoring temperature metrics and identifying or predicting the onset of a dry out state, and temperature modulation mechanism may be controlled to cause an increase in the temperature of the heat pipe or vapor chamber. By controlling a temperature modulation mechanism to increase the operating temperature, the viscosity of the liquid in the thermal management approach is decreased, which improves its capillary flow and return rate back to the evaporator. By leveraging this temperature-dependent behavior, this thermal control approach may restore cooling capacity by managing the thermal management approach temperature due to a dry out state, and reduce or minimize the computing device performance degradation associated with a dry out state.

公开(公告)号：US20250105962A1

公开(公告)日：2025-03-27

申请号：US18471334

申请日：2023-09-21

Applicant: Intel Corporation

Inventor： Sagar DHAKAL ,  Yang-Seok CHOI ,  Jan SCHRECK ,  Thushara HEWAVITHANA ,  Nicholas WHINNETT

IPC: H04L5/00 ,  H04L25/02

Abstract: A radio communication device may include a memory; and a processor configured to: perform a plurality of channel estimations based on a received radio signal comprising a plurality of reference signals of a plurality of mobile radio communication devices, wherein each channel estimation of the plurality of channel estimations is for a respective mobile radio communication device of the plurality of communication devices; determine a residual signal for the plurality of mobile radio communication devices based on the plurality of channel estimations; and estimate channel information for at least one mobile radio communication device from the plurality of radio communication device based on the residual signal and an estimated power delay profile.

公开(公告)号：US20250105222A1

公开(公告)日：2025-03-27

申请号：US18475326

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Gang Duan ,  Yosuke Kanaoka ,  Minglu Liu ,  Srinivas V. Pietambaram ,  Brandon C. Marin ,  Bohan Shan ,  Haobo Chen ,  Benjamin T. Duong ,  Jeremy Ecton ,  Suddhasattwa Nad

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/29 ,  H01L23/538

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer including first dies in a first insulating material; a second layer on the first layer, the second layer including second dies and third dies in a second insulating material, the second dies having a first thickness, the third dies having a second thickness different than the first thickness, and the second dies and the third dies having a surface, wherein the surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm2) and 9,000 mm2; and a redistribution layer (RDL) between the first layer and the second layer, the RDL including conductive pathways through the RDL, wherein the first dies are electrically coupled to the second dies and the third dies by the conductive pathways through the RDL and by interconnects.

公开(公告)号：US20250104179A1

公开(公告)日：2025-03-27

申请号：US18905803

申请日：2024-10-03

Applicant: Intel Corporation

Inventor： Altug Koker ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Josh Mastronarde ,  Naveen Matam ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC: G06T1/20 ,  G06F13/40

Abstract: A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, cache or DRAM memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

公开(公告)号：US20250103965A1

公开(公告)日：2025-03-27

申请号：US18971998

申请日：2024-12-06

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Marcos Carranza ,  Thomas Willhalm ,  Patrick Connor

IPC: G06N20/00 ,  G06F16/334

Abstract: An apparatus includes a host interface, a network interface, and programmable circuitry communicably coupled to the host interface and the network interface, the programmable circuitry comprising one or more processors are to implement network interface functionality and are to receive a prompt directed to an artificial intelligence (AI) model hosted by a host device communicably coupled to the host interface, apply a prompt tuning model to the prompt to generate an initial augmented prompt, compare the initial augmented prompt for a match with stored data of a prompt augmentation tracking table comprising real-time datacenter trend data and cross-network historical augmentation data from programmable network interface devices in a datacenter hosting the apparatus, generate, in response to identification of the match with the stored data, a final augmented prompt based on the match, and transmit the final augmented prompt to the AI model.