公开(公告)号：US20160055056A1

公开(公告)日：2016-02-25

申请号：US14729656

申请日：2015-06-03

申请人： Jong-Pil SON ,  Chul-Woo PARK ,  Seong-Jin JANG ,  Hoi-Ju CHUNG ,  Sang-Uhn CHA

发明人： Jong-Pil SON ,  Chul-Woo PARK ,  Seong-Jin JANG ,  Hoi-Ju CHUNG ,  Sang-Uhn CHA

IPC分类号： G06F11/10 ,  G11C29/52

CPC分类号： G06F11/1008 ,  G06F11/1004 ,  G06F11/1024 ,  G06F11/1068 ,  G06F11/1666 ,  G11C2029/0411

摘要： A memory device having an error notification function includes an error correction code (ECC) engine detecting and correcting an error bit by performing an ECC operation on data of the plurality of memory cells, and an error notifying circuit configured to output an error signal according to the ECC operation. The ECC engine outputs error information corresponding to the error bit corresponding to a particular address corrected by the ECC operation. The error notifying circuit may output the error signal when the particular address is not the same as any one of existing one or more failed addresses.

摘要翻译： 具有错误通知功能的存储装置包括通过对多个存储单元的数据执行ECC操作来检测和校正错误位的纠错码（ECC）引擎，以及错误通知电路，配置为根据 ECC操作。 ECC引擎输出与通过ECC操作校正的特定地址相对应的错误位对应的错误信息。 当特定地址与现有一个或多个故障地址中的任一个不同时，错误通知电路可以输出错误信号。

公开(公告)号：US09269457B2

公开(公告)日：2016-02-23

申请号：US13777428

申请日：2013-02-26

申请人： Jeong-kyoum Kim ,  Seok-hun Hyun ,  Jung-hwan Choi ,  Seong-jin Jang

发明人： Jeong-kyoum Kim ,  Seok-hun Hyun ,  Jung-hwan Choi ,  Seong-jin Jang

IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C29/44 ,  G11C5/04 ,  G11C11/40

CPC分类号： G11C17/18 ,  G11C5/04 ,  G11C11/40 ,  G11C17/16 ,  G11C29/04 ,  G11C29/44 ,  G11C29/76 ,  G11C29/78 ,  G11C29/789 ,  G11C2029/4402

摘要： A memory device capable of rescuing defective characteristics that occur after packaging includes a memory cell array including a plurality of memory cells and an antifuse circuit unit including at least one antifuse. The antifuse circuit unit stores a defective cell address of the memory cell array in the at least one antifuse and reads the defective cell address to an external source. The antifuse circuit unit stores a defective characteristic code in the at least one antifuse, wherein the defective characteristic code is related to at least one of a timing parameter spec., a refresh spec., an input/output (I/O) trigger voltage spec., and a data training spec. of the memory device, and outputs the defective characteristic code to an external source.

公开(公告)号：US08891324B2

公开(公告)日：2014-11-18

申请号：US13915338

申请日：2013-06-11

申请人： Chul-woo Yi ,  Seong-jin Jang ,  Jin-seok Kwak ,  Tai-young Ko ,  Joung-yeal Kim ,  Sang-yun Kim ,  Sang-kyun Park ,  Jung-bae Lee

发明人： Chul-woo Yi ,  Seong-jin Jang ,  Jin-seok Kwak ,  Tai-young Ko ,  Joung-yeal Kim ,  Sang-yun Kim ,  Sang-kyun Park ,  Jung-bae Lee

IPC分类号： G11C7/00 ,  G11C5/06 ,  G11C7/06 ,  H01L27/02 ,  H01L27/105 ,  G11C7/18 ,  G11C11/4091 ,  H01L27/108

CPC分类号： G11C5/063 ,  G11C7/062 ,  G11C7/065 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10885 ,  H01L27/10897 ,  Y10T29/41

摘要： A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.

摘要翻译： 一种具有开放位线存储器结构的半导体存储器件，其中除去边缘伪存储器块，所述半导体存储器件包括存储器块，边沿读出放大块，其包括第一读出放大器，所述第一读出放大器具有第一位线，第一互补位线和 第一放大电路，包括具有第一尺寸的第一晶体管，中央读出放大块，包括具有第二位线的第二读出放大器，第二互补位线和第二放大电路，所述第二放大电路包括第二晶体管， 电容器块电连接到边缘检测放大块。

公开(公告)号：US20130272047A1

公开(公告)日：2013-10-17

申请号：US13915338

申请日：2013-06-11

申请人： Chul-woo YI ,  Seong-jin JANG ,  Jin-seok KWAK ,  Tai-young KO ,  Joung-yeal KIM ,  Sang-yun KIM ,  Sang-kyun PARK ,  Jung-bae LEE

发明人： Chul-woo YI ,  Seong-jin JANG ,  Jin-seok KWAK ,  Tai-young KO ,  Joung-yeal KIM ,  Sang-yun KIM ,  Sang-kyun PARK ,  Jung-bae LEE

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  G11C7/062 ,  G11C7/065 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10885 ,  H01L27/10897 ,  Y10T29/41

摘要： A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.

摘要翻译： 一种具有开放位线存储器结构的半导体存储器件，其中除去边缘伪存储器块，所述半导体存储器件包括存储器块，边沿读出放大块，其包括第一读出放大器，所述第一读出放大器具有第一位线，第一互补位线和 第一放大电路，包括具有第一尺寸的第一晶体管，中央读出放大块，包括具有第二位线的第二读出放大器，第二互补位线和第二放大电路，所述第二放大电路包括第二晶体管， 电容器块电连接到边缘检测放大块。

公开(公告)号：US08335291B2

公开(公告)日：2012-12-18

申请号：US12929627

申请日：2011-02-04

申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

IPC分类号： H04L7/00

CPC分类号： G11C7/22 ,  H03K19/0966 ,  H04L7/0008 ,  H04L7/033 ,  H04L7/10

摘要： A semiconductor device, a parallel interface system and methods thereof are provided. The example semiconductor device may include a reference clock transmitting block generating a reference clock signal, a plurality of first transceiver blocks, each of the plurality of first transceiver blocks transmitting at least one parallel data bit signal based on one of a plurality of phase-controlled transmitting sampling clock signals and a per-pin deskew block controlling a phase of a transmitting sampling clock signal to generate the phase-controlled sampling clock signals for the respective plurality of transceiver blocks, the per-pin deskew block controlling the phase of each phase-controlled transmitting sampling clock signal based on a phase skew between a given training data bit signal, among a plurality of training data bit signals, corresponding to a given first transceiver block and the reference clock signal in a first operation mode, and based on phase skew information relating to a phase skew between a given parallel data bit signal of the at least one parallel data bit signal and the reference clock signal in a second operation mode. An example method may include reducing skew based on a comparison between a plurality of transmitted training data bit signals and a corresponding plurality of received training data bit signals in a first mode of operation and reducing skew based on received phase skew information relating to a phase skew difference between a reference signal and a parallel data bit signal in a second mode of operation.

摘要翻译： 提供半导体器件，并行接口系统及其方法。 示例性半导体器件可以包括产生参考时钟信号的参考时钟发送块，多个第一收发器块，多个第一收发器块中的每一个基于多个相位控制的多个第一收发器块中的一个发送至少一个并行数据位信号 传输采样时钟信号和控制发射采样时钟信号的相位的每引脚偏移校正块，以产生相应的多个收发器模块的相位控制的采样时钟信号，每个引脚的去偏移块控制每个相位 - 基于相对于给定的第一收发器块的多个训练数据位信号中的给定训练数据位信号与第一操作模式中的参考时钟信号之间的相位偏移以及基于相位偏移的受控发送采样时钟信号 与至少一个并行数据的给定并行数据位信号之间的相位偏移有关的信息 在第二操作模式中的位信号和参考时钟信号。 示例性方法可以包括基于在第一操作模式中的多个发送的训练数据比特信号与对应的多个接收的训练数据比特信号之间的比较来减少偏斜，并且基于接收到的相位偏移相关的相位偏移信息减少偏斜 在第二操作模式中参考信号和并行数据位信号之间的差异。

公开(公告)号：US08284624B2

公开(公告)日：2012-10-09

申请号：US12691910

申请日：2010-01-22

申请人： Ki-Heung Kim ,  Yong-Ho Cho ,  Ji-Hoon Lim ,  Seong-Jin Jang ,  Tae-Yoon Lee

发明人： Ki-Heung Kim ,  Yong-Ho Cho ,  Ji-Hoon Lim ,  Seong-Jin Jang ,  Tae-Yoon Lee

IPC分类号： G11C7/04

CPC分类号： G11C7/04 ,  G01R19/16552 ,  G11C5/147 ,  H03K5/2481

摘要： A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.

摘要翻译： 提供了一种电平检测器，包括电平检测器的内部电压发生器和包括内部电压发生器的半导体存储器件。 内部电压发生器包括电平检测器，其将与温度变化的阈值电压与内部电压进行比较以输出比较电压;以及内部电压驱动器，其响应于比较电压调节外部电源电压并且输出内部电压 。

公开(公告)号：US20120051164A1

公开(公告)日：2012-03-01

申请号：US13219998

申请日：2011-08-29

申请人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Ju-Seop Park

发明人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Ju-Seop Park

IPC分类号： G11C29/04 ,  H01L21/336 ,  G11C7/00 ,  H01L27/088

CPC分类号： G11C11/405 ,  G11C17/16 ,  G11C17/165 ,  H01L27/101 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/7835

摘要： A memory cell includes a selection transistor on a substrate and an antifuse on the substrate. The selection transistor includes a first gate connected to a read word line, a first gate insulation layer that insulates the first gate from the substrate, a first source region connected to a bit line, and a first drain region, an impurity concentration of the first drain region being lower than an impurity concentration of the first source region. The antifuse includes a first electrode connected to a program word line and a second electrode connected to the selection transistor.

摘要翻译： 存储单元包括衬底上的选择晶体管和衬底上的反熔丝。 选择晶体管包括连接到读字线的第一栅极，将第一栅极与衬底绝缘的第一栅极绝缘层，连接到位线的第一源极区域和第一漏极区域，第一漏极区域的杂质浓度 漏极区域低于第一源极区域的杂质浓度。 反熔丝包括连接到编程字线的第一电极和连接到选择晶体管的第二电极。

公开(公告)号：US20110249513A1

公开(公告)日：2011-10-13

申请号：US13158616

申请日：2011-06-13

申请人： Seung-Jun Bae ,  Seong-Jin Jang

发明人： Seung-Jun Bae ,  Seong-Jin Jang

IPC分类号： G11C7/10

CPC分类号： H03M5/145

摘要： DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.

摘要翻译： 通过发送伪数据的前导码来发送DC平衡编码数据，该伪数据的前导码被配置为提供给定逻辑值的中间位数，该给定逻辑值是给定逻辑值的至少一位，但小于给定逻辑值的最大位数 DC平衡编码数据中的逻辑值，从而减少由DC平衡编码数据的第一字的传输引起的同时开关噪声。 前导码可以包含固定和/或可变虚拟数据的一个或多个单词。

公开(公告)号：US07961121B2

公开(公告)日：2011-06-14

申请号：US12824156

申请日：2010-06-26

申请人： Seung-Jun Bae ,  Seong-Jin Jang

发明人： Seung-Jun Bae ,  Seong-Jin Jang

IPC分类号： H03M5/00

CPC分类号： H03M5/145

摘要： DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.

摘要翻译： 通过发送伪数据的前导码来发送DC平衡编码数据，该伪数据的前导码被配置为提供给定逻辑值的中间位数，该给定逻辑值是给定逻辑值的至少一位，但小于给定逻辑值的最大位数 DC平衡编码数据中的逻辑值，从而减少由DC平衡编码数据的第一字的传输引起的同时开关噪声。 前导码可以包含固定和/或可变虚拟数据的一个或多个单词。

公开(公告)号：US20110128170A1

公开(公告)日：2011-06-02

申请号：US12923858

申请日：2010-10-12

申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

IPC分类号： H03M7/00

CPC分类号： H03K19/00346 ,  H04L25/03866 ,  H04L25/14 ,  H04L25/4908

摘要： Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

摘要翻译： 提供半导体器件，包括所述半导体器件的系统及其方法。 半导体器件的示例可以接收被调度用于发送的数据，对接收到的数据内的比特顺序进行加扰，根据给定的伪随机序列排列的加扰顺序。 所接收的数据可以是平衡的，使得等于第一逻辑电平的接收数据内的第一比特数与等于第二逻辑电平的接收数据中的第二比特数之间的差异低于阈值。 然后可以发送平衡和加扰的接收数据。 示例半导体器件可以以任何顺序执行加扰和平衡操作。 类似地，在接收端，另一个半导体器件可以通过对发送的数据进行解扰和不平衡来解码原始数据。 可以基于发送的数据被加扰和平衡的顺序以顺序执行解扰和不平衡操作。