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    ANTI-FUSE
    1.
    发明申请
    ANTI-FUSE 审中-公开
    防静电

    公开(公告)号：US20090026576A1

    公开(公告)日：2009-01-29

    申请号：US11782154

    申请日：2007-07-24

    Applicant: Kuang-Yeh Chang ,  Shing-Ren Sheu ,  Chung Jen Ho

    Inventor： Kuang-Yeh Chang ,  Shing-Ren Sheu ,  Chung Jen Ho

    IPC: H01L29/00 ,  H01L21/336

    CPC classification number: H01L23/5252 ,  H01L21/26586 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An anti-fuse is provided. The anti-fuse includes a substrate, a gate disposed over the substrate, a gate dielectric layer sandwiched between the substrate and the gate, and two source/drain regions in the substrate at respective sides of the gate. The gate and the substrate have the same conductive type, but the conductive type of the gate and the substrate is different from that of the two source/drain regions.

    Abstract translation: 提供反熔丝。 反熔丝包括衬底，设置在衬底上的栅极，夹在衬底和栅极之间的栅极电介质层以及在栅极的相应侧的衬底中的两个源极/漏极区域。 栅极和衬底具有相同的导电类型，但是栅极和衬底的导电类型与两个源极/漏极区的导电类型不同。

    Variable work function transistor high density mask ROM
    2.
    发明授权
    Variable work function transistor high density mask ROM 失效

    公开(公告)号：US5942786A

    公开(公告)日：1999-08-24

    申请号：US767824

    申请日：1996-12-17

    Applicant: Shing-Ren Sheu ,  Cheng-Chih Kung

    Inventor： Shing-Ren Sheu ,  Cheng-Chih Kung

    IPC: H01L27/112 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    CPC classification number: H01L27/112

    Abstract: A mask ROM stores information by selecting the work function of the gates of each FET in an array of FETs. The polysilicon gates of some of the FETs are doped N-type and the gates of the other FETs are doped P-type to form gates having different work functions, thereby forming FETs having different threshold voltages. The ROM consists of a parallel array of buried N.sup.+ bit lines formed in the substrate, a gate oxide layer deposited over the bit lines and a layer of polysilicon deposited on the gate oxide. The polysilicon is blanket doped P-type and then an encoding mask is formed, with openings in the encoding mask exposing regions of the polysilicon to be formed into gates of FETs with low threshold voltages. Either arsenic or phosphorus is doped into the polysilicon through the mask openings. The mask is removed, a layer of conductive material such as tungsten silicide is deposited and the polysilicon and the conductive material are formed into word lines for the ROM. The word lines of the ROM serve as gates for the FETs and the bit lines serve as sources and drains for the FETs.

    Stacked CVD oxide architecture multi-state memory cell for mask read-only memories
    3.
    发明授权
    Stacked CVD oxide architecture multi-state memory cell for mask read-only memories 失效
    堆叠CVD氧化物架构用于掩模只读存储器的多状态存储单元

    公开(公告)号：US5576573A

    公开(公告)日：1996-11-19

    申请号：US454701

    申请日：1995-05-31

    Applicant: Kuan-Cheng Su ,  Shing-Ren Sheu

    Inventor： Kuan-Cheng Su ,  Shing-Ren Sheu

    IPC: H01L27/112 ,  H01L29/423 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    CPC classification number: H01L27/112 ,  H01L29/42368 ,  Y10S438/981

    Abstract: A multi-state memory cell for a mask ROM device. Source/drain regions are arranged on a substrate as strips extending along a first direction on the plane of the substrate and bit lines. Gate oxide layers are arranged on the substrate as strips extending along a second direction. Gate electrodes are each formed on top of each of the gate oxide layers as strips extending along the second direction. The gate oxide layers have a number of selected thickness' arranged in a differential series. Each of the transistor channel regions, together with their corresponding one of the neighboring source/drain pair, the gate oxide layer on top, and the gate electrodes further on top thereof constitute one of the memory cells that can have its threshold voltage varied among the differential series of thicknesses allowing for the storage of a multi-bit equivalent of memory content for the memory cell.

    Abstract translation: 一种用于掩模ROM器件的多状态存储单元。 源极/漏极区域沿着衬底和位线的平面上沿着第一方向延伸的条带布置在衬底上。 栅极氧化物层沿着第二方向布置在基板上。 栅极电极分别形成在每个栅极氧化物层的顶部上，作为沿第二方向延伸的条带。 栅极氧化物层具有多个选定的厚度，以差分系列排列。 每个晶体管沟道区以及它们相应的一个源极/漏极对，顶部的栅极氧化物层和进一步在其顶部的栅电极构成一个存储单元，其可以使其阈值电压在 差分系列的厚度允许存储用于存储器单元的多位等效的存储器内容。

    Semiconductor read-only memory device and method of fabricating the same
    6.
    发明授权
    Semiconductor read-only memory device and method of fabricating the same 有权
    半导体只读存储器件及其制造方法

    公开(公告)号：US06350654B1

    公开(公告)日：2002-02-26

    申请号：US09215618

    申请日：1998-12-17

    Applicant: Shing-Ren Sheu ,  Chung-Hsien Wu ,  Chih-Ming Huang

    Inventor： Shing-Ren Sheu ,  Chung-Hsien Wu ,  Chih-Ming Huang

    IPC: H01L21336

    CPC classification number: H01L27/1126 ,  H01L27/105 ,  H01L27/11293

    Abstract: A semiconductor read-only memory (ROM) and a method of fabricating the same are provided. The ROM device is structured in such a manner that allows the fabrication to include a fewer number of mask processes. This makes it more cost effective and allows a cycle time that is shorter than that of the prior art. Moreover, the particular structure of the ROM device makes punchthrough less likely to occur between any neighboring pairs of the buried bit lines when the ROM device is further scaled down. The ROM device is constructed on a semiconductor substrate which is partitioned into a peripheral region and a cell region. A plurality of STI structures are formed at predefined locations in both the peripheral region and the cell region. Immediately after this, a first ion-implantation process can be performed on the cell region to form a plurality of buried bit lines. Subsequently, the dielectric isolation layers in all of the STI structures in the cell region are removed, leaving a plurality of empty trenches behind. A conformal insulating layer and a conductive layer are then successively formed over the wafer, and the conductive layer is further selectively removed to form a word line in the cell region and a gate in the peripheral region. In the code implantation process, selected channel regions between the buried bit lines are doped with impurities for code implantation of data into the ROM device.

    Abstract translation: 提供半导体只读存储器（ROM）及其制造方法。 ROM器件以允许制造包括更少数量的掩模处理的方式构造。 这使得它更具成本效益并且允许比现有技术更短的循环时间。 此外，当ROM器件进一步缩小时，ROM器件的特定结构使得在任何相邻的掩埋位线对之间不太可能发生穿透。 ROM器件被构造在被划分成周边区域和单元区域的半导体衬底上。 在周边区域和单元区域中的预定位置处形成多个STI结构。 此后，可以在单元区域上进行第一离子注入工艺以形成多个掩埋位线。 随后，去除单元区域中所有STI结构中的介电隔离层，留下多个空槽。 然后在晶片上连续地形成保形绝缘层和导电层，并且进一步选择性地去除导电层，以在单元区域中形成字线，并在外围区域形成栅极。 在代码注入过程中，掩埋位线之间的选定沟道区域掺杂有用于将数据代码注入到ROM器件中的杂质。

    CVD oxide coding method for ultra-high density mask read-only-memory (ROM)
    7.
    发明授权
    CVD oxide coding method for ultra-high density mask read-only-memory (ROM) 失效
    用于超高密度掩模只读存储器（ROM）的CVD氧化物编码方法

    公开(公告)号：US5597753A

    公开(公告)日：1997-01-28

    申请号：US364318

    申请日：1994-12-27

    Applicant: Shing-Ren Sheu ,  Kuan-Cheng Su ,  Chen-Hui Chung ,  Yi-Chung Sheng

    Inventor： Shing-Ren Sheu ,  Kuan-Cheng Su ,  Chen-Hui Chung ,  Yi-Chung Sheng

    IPC: H01L21/8246

    CPC classification number: H01L27/11246 ,  Y10S438/981

    Abstract: An improved Read-Only-Memory (ROM) structure and a method of manufacturing said ROM device structure having an ultra-high-density of coded ROM cells, was achieved. The array of programmed ROM cells are composed of a single field effect transistor (FET) in each ROM cell. The improved ROM process utilizes the patterning of a ROM code insulating layer over each coded FET (cell) that is selected to remain in an off-state (nonconducting) when a gate voltage is applied. The remaining FETs (cells) have a thin gate oxide which switch to the on-state (conducting) when a gate voltage is applied. The thick ROM code insulating layer eliminates the need to code the FETs in the ROM memory cells by conventional high dose ion implantation. This eliminated the counter-doping of the buried bit lines by the implantation allowing for much tighter ground rules for the spacing between buried bit line. The elimination of the implant also reduces substantially the stand-by leakage current that is so important in battery operated electronic equipment, such as lap-top computers. The gate capacitance of the off-state cells is also substantially reduced because of the thick insulating layer, thereby reducing the RC time delay in the word lines and improving circuit performance.

    Abstract translation: 实现了改进的只读存储器（ROM）结构和制造具有超高密度编码ROM单元的所述ROM器件结构的方法。 编程ROM单元的阵列由每个ROM单元中的单个场效应晶体管（FET）构成。 改进的ROM处理利用在施加栅极电压时选择为保持在截止状态（非导通）的每个编码的FET（单元）上的ROM代码绝缘层的图案化。 当施加栅极电压时，剩余的FET（单元）具有薄的栅极氧化物，其切换到导通状态（导通）。 粗ROM代码绝缘层消除了通过常规高剂量离子注入对ROM存储单元中的FET进行编码的需要。 这通过注入消除了掩埋位线的反掺杂，允许掩埋位线之间的间隔更紧密的基本规则。 植入物的消除也大大降低了备用泄漏电流，这在电池供电的电子设备如笔记本电脑中如此重要。 由于厚的绝缘层，断态单元的栅极电容也显着减小，从而减小了字线中的RC时间延迟并提高了电路性能。

    Post-titanium nitride mask ROM programming method
    8.
    发明授权
    Post-titanium nitride mask ROM programming method 失效
    后氮化钛掩模ROM编程方法

    公开(公告)号：US5488009A

    公开(公告)日：1996-01-30

    申请号：US344004

    申请日：1994-11-23

    Applicant: Chen-Chiu Hsue ,  Yi-Chung Shen ,  Shing-Ren Sheu ,  Chen-Hui Chung

    Inventor： Chen-Chiu Hsue ,  Yi-Chung Shen ,  Shing-Ren Sheu ,  Chen-Hui Chung

    IPC: H01L21/8246 ,  H01L27/112

    CPC classification number: H01L27/1126 ,  H01L27/112 ,  Y10S257/915

    Abstract: A method of manufacturing a code pattern on a semiconductor substrate with an array of substantially parallel buried bit lines integral therewith and with word lines above the buried bit lines, includes: forming a titanium nitride layer above the word lines, forming and patterning a code mask above the titanium nitride layer, implanting impurities into the substrate through openings in the code mask to form the code pattern, and performing rapid thermal annealing of the implant. The step height of the titanium nitride layer is employed to form the code identification on the substrate.

    Abstract translation: 一种在半导体衬底上制造具有与其一体的基本上平行的掩埋位线阵列和掩埋位线之上的字线的阵列的方法，包括：在字线之上形成氮化钛层，形成码图掩模 在氮化钛层之上，通过编码掩模中的开口将杂质注入到衬底中，以形成编码图案，并对植入物进行快速热退火。 氮化钛层的台阶高度用于在基板上形成代码识别。

    Field effect transistor with recessed buried source and drain regions
    9.
    发明授权
    Field effect transistor with recessed buried source and drain regions 失效
    具有埋入式源极和漏极区域的场效应晶体管

    公开(公告)号：US5382534A

    公开(公告)日：1995-01-17

    申请号：US254534

    申请日：1994-06-06

    Applicant: Shing-Ren Sheu ,  Kuan-Cheng Su ,  Chen-Hui Chung

    Inventor： Shing-Ren Sheu ,  Kuan-Cheng Su ,  Chen-Hui Chung

    IPC: H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265

    CPC classification number: H01L29/66636 ,  H01L29/0847 ,  H01L29/1083

    Abstract: The invention describes recessed buried conductive regions formed in a trench in the substrate that provides a smooth surface topology, smaller devices and improved device performance. The buried regions have two conductive regions, the first on the trench sidewalls, the second on the trench bottom. In addition, two buried layers are formed between adjacent buried conductive regions: a threshold voltage layer near the substrate surface and an anti-punchthrough layer formed at approximately the same depth as the conductive regions on the trench bottoms. The first conductive region and the anti-punchthrough layer have the effect of increasing the punchthru voltage without increasing the threshold voltage. The first and second regions also lowers the resistivity of the buried regions allowing use of smaller line pitches and therefore smaller devices. Overall, the recessed conductive regions and the two buried layers allow the formation of smaller devices with improved performance.

    Abstract translation: 本发明描述了形成在衬底中的沟槽中的凹入的埋入导电区域，其提供了平滑的表面拓扑，较小的器件和改进的器件性能。 掩埋区域具有两个导电区域，第一个在沟槽侧壁上，第二个在沟槽底部。 此外，在相邻的掩埋导电区域之间形成两个掩埋层：在衬底表面附近的阈值电压层和形成在与沟槽底部上的导电区域大致相同深度的抗穿通层。 第一导电区域和抗穿通层具有增加穿透电压而不增加阈值电压的效果。 第一和第二区域也降低了掩埋区域的电阻率，从而允许使用较小的线间距并因此使用较小的器件。 总的来说，凹入的导电区域和两个掩埋层允许形成具有改进的性能的较小的器件。

    Device under test array for identifying defects
    10.
    发明授权
    Device under test array for identifying defects 有权
    用于识别缺陷的被测设备

    公开(公告)号：US07859285B2

    公开(公告)日：2010-12-28

    申请号：US12145518

    申请日：2008-06-25

    Applicant: Shing-Ren Sheu ,  Chun-Chieh Huang

    Inventor： Shing-Ren Sheu ,  Chun-Chieh Huang

    IPC: G01R31/02 ,  G01R31/26

    CPC classification number: G01R31/2884 ,  G01R31/2831

    Abstract: A device under test (DUT) array provides defect information rapidly and systematically. The DUT array includes a plurality of test units arranged in a matrix, a plurality of bit lines and a plurality of word lines. Each test unit has a first terminal and a second terminal. Each second terminal of the test unit is electrically connected to a ground point. The first terminals of the test units are electrically connected to the bit lines. The word lines are coupled to the test units. Defects in the each test unit can be identified by providing voltages to the bit lines and the word lines. Accordingly, defects in various devices of an integrated circuit can be detected rapidly and systematically by applying signals to the DUT array.

    Abstract translation: 被测器件（DUT）阵列快速有系统地提供缺陷信息。 DUT阵列包括以矩阵，多个位线和多个字线布置的多个测试单元。 每个测试单元具有第一端子和第二端子。 测试单元的每个第二端子电连接到接地点。 测试单元的第一个端子电连接到位线。 字线耦合到测试单元。 可以通过向位线和字线提供电压来识别每个测试单元中的缺陷。 因此，可以通过向DUT阵列施加信号来快速且系统地检测集成电路的各种装置中的缺陷。

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